Chinese semiconductor industry

latenlazy said:

In transistor density.

Click to expand...

So you agree Intel 7 has equivalent density as TSMC & Samsung 7nm? Intel is also already in risk production of Intel 4, whether their volume ramp later this year would be smooth is the big question.

latenlazy said:

Not the same thing as transistor performance.

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true. transistor density don't equal performance. But transistor density is still the standard industry metric to benchmark logic process nodes. With 2D shrink slowing, there is more emphasis on using PPA to quantify node-over-node improvement instead of transistor density.

latenlazy said:

Latter is more important. Intel’s chase to maintain density at each node shrink actually ended up slowing it down on matching transistor performance.

Click to expand...

What exact metric are you referring to when you say 'performance'? Could you share where would Intel 7 rank on the totem pole? Would be good if you could also share performance comparison that lead to your conclusion. Thanks.

PopularScience said:

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我觉得光刻机这么复杂的系统，调试过程中出现问题很正常。没必要对清华冷嘲热讽的。何况具体情况未知。让子弹再飞一会儿吧。。。

不负责任转载水木BBS上另一篇所谓的辟谣贴。就当是听听另一方的声音吧。

“ 所谓清华双工件台拉胯纯属造谣

1. 清华作为02专项子项目承担方，研究课题早已通过验收好多年了；
2. 研究结项之后，课题负责人朱教授的公司华卓负责产业化；
3. 所谓最近“双工件台拉胯”谣言的根据，就是华卓在上市材料中，把双工件台从主营业务中拿掉了；
4. 拿掉的原因华卓解释的很清楚，上海微电子是光刻机集成商，上微光刻机整机无法规模出货，工件台营收自然好不了，在上市材料里面作为主营业务不合适；
5. 至于上海微电子的光刻机卡在哪个部件了，这个部件哪个公司哪个学校负责，只能呵呵了。 ”

Click to expand...

bro, sorry to be a bother, but I couldn't tell from the translation where it says U-precision is not a bottleneck for SMEE. Could you specify which bullet number you are referring to. #5 implies U-Precision is not the bottleneck, but #1-4 doesn't really seem to support it?

Google Translation:
I think it's normal for a system of such a complex photolithography machine to have problems in the debugging process. There is no need to cynicize Tsinghua University. What's more, the specific situation is unknown. Let the bullet fly for a while...

Irresponsibly reprint another so-called rumor refutation post on Shuimu BBS. Just listen to the voice of the other party.

"The so-called Tsinghua dual-workpiece platform pulling the crotch is purely a rumor.

1. As the bearer of the 02 special sub-project, Tsinghua University has been accepted for many years.

2. After the completion of the research, Huazhuo, the company of Professor Zhu, is responsible for industrialization.

3. The basis for the so-called recent rumor of "double-workpiece table pulling the crotch" is that Huazhuo removed the double-work table from the main business in the listed materials;

4. The reason for removing it is very clear. Shanghai Microelectronics is an integrator of lithography machines. The whole machine on-scale shipment of the upper micro-lithography machine cannot be shipped on a large scale, and the revenue of the workpiece counter is naturally not good. It is not suitable to be used as the main business in the listed materials.

5. As for which part of Shanghai Microelectronics lithography machine is stuck in, and which company and school is responsible for this part, I can only hehe. ”

ASML pushing back?

hvpc said:

bro, sorry to be a bother, but I couldn't tell from the translation where it says U-precision is not a bottleneck for SMEE. Could you specify which bullet number you are referring to. #5 implies U-Precision is not the bottleneck, but #1-4 doesn't really seem to support it?

Google Translation:
I think it's normal for a system of such a complex photolithography machine to have problems in the debugging process. There is no need to cynicize Tsinghua University. What's more, the specific situation is unknown. Let the bullet fly for a while...

Irresponsibly reprint another so-called rumor refutation post on Shuimu BBS. Just listen to the voice of the other party.

"The so-called Tsinghua dual-workpiece platform pulling the crotch is purely a rumor.

1. As the bearer of the 02 special sub-project, Tsinghua University has been accepted for many years.

2. After the completion of the research, Huazhuo, the company of Professor Zhu, is responsible for industrialization.

3. The basis for the so-called recent rumor of "double-workpiece table pulling the crotch" is that Huazhuo removed the double-work table from the main business in the listed materials;

4. The reason for removing it is very clear. Shanghai Microelectronics is an integrator of lithography machines. The whole machine on-scale shipment of the upper micro-lithography machine cannot be shipped on a large scale, and the revenue of the workpiece counter is naturally not good. It is not suitable to be used as the main business in the listed materials.

5. As for which part of Shanghai Microelectronics lithography machine is stuck in, and which company and school is responsible for this part, I can only hehe. ”

Click to expand...

no 4. SMEE didn't progress well, so the double stage component revenue didn't list in the IPO document.

no 5. 'hehe' implied they were not the bottleneck

hvpc said:

So you agree Intel 7 has equivalent density as TSMC & Samsung 7nm? Intel is also already in risk production of Intel 4, whether their volume ramp later this year would be smooth is the big question.

Click to expand...

Whether I agree or not that’s the objective fact. But there’s a reason why serious semis people don’t see Intel’s 10nm as equivalent in performance to TSMC’s 7nm. Trying to shift the attention to density is little more than a bit of Intel marketing speak to salvage Intel’s sliding reputation.

To be clear I don’t personally hold the view that Intel is incapable of catching up to TSMC. They fell behind because their vertical business model requires a level of fab utilization and wafer utilization efficiency that basically forced them to adopt requirements to preserve density scaling along with node shrinks. The math behind the quantity of chip sales to keep fab upgrades economically worthwhile was brutal, but while Intel was winning with the Wintel monopoly they were able to turn that business model into a finely tuned tick tocking machine. Mobile crowding out PCs really hurt, and really tightened the pressure to keep density scaling apace with the node shrink game (smaller future sales growth, more expensive fab upgrades, less margins to relax utilization efficiencies). But just as ARM was eating away Intel’s future chip sales what really came to a head for them was the physical realities of quantum limitations at smaller feature sizes and FinFET transistor design. Essentially their business model became misaligned from engineering realities. TSMC and Samsung did not have such stringent density requirements, which is one reason they managed to get ahead (though not the only reason). I’ll get to Intel’s 4 nm a bit later.

hvpc said:

true. transistor density don't equal performance. But transistor density is still the standard industry metric to benchmark logic process nodes. With 2D shrink slowing, there is more emphasis on using PPA to quantify node-over-node improvement instead of transistor density.

Click to expand...

No. The first order benchmark was always switch speed and switch efficiency. Density was always secondary, but used to be treated as synonymous because all three parameters kept a very tight relationship. That changed with FinFET and with smaller nodes. Today they’re becoming somewhat decoupled. But that’s not just because of 2D node shrinks slowing. The particulars of basic technical parameters have changed post FinFET transition. I think you got the story a bit backward there.

hvpc said:

What exact metric are you referring to when you say 'performance'?

Click to expand...

See above.

hvpc said:

Could you share where would Intel 7 rank on the totem pole? Would be good if you could also share performance comparison that lead to your conclusion. Thanks.

Click to expand...

My guess, having not checked the technical details, is that Intel 7 is probably roughly equivalent to TSMC 7. But interestingly enough Intel 7 also relaxed its density scaling requirements from Intel 10. Curious!

This is where we get to the prospects for Intel 4. Intel separated its fab and design business to try to shift their business model to better allow it to chase the node shrink and fabrication innovation game. But to do so, they need to be able to find clients who will take on the risk of adopting trial phases of their new nodes in order to subsidize fab development toward mass production for their own chip products. Word on the street right now is that Intel is struggling mightily with the execution details for this part of their new strategy. So while I actually have considerable confidence in Intel’s engineering chops, I am quite a bit more ambivalent about whether the business side of the equation will hold up its end to continue supporting their efforts in the node shrink game.

Why did I bother to go on this long tirade? Because there are some broader implications here for how we think about SMIC’s own efforts. Intel’s ability to continue to push further node shrinks at the same clip as its competition is as much dependent on business questions as it is on engineering ones, and on the business front Intel’s prospects are being challenged significantly by its ability to compete with TSMC for clients. SMIC would be in the *exact* same situation as Intel today, were it not for two very big intervening factors: 1) potentially “wasteful” levels of state support, 2) (imo the far more important factor) a massive captive by default market from the US’s tech bans where SMIC will face almost no competition from acquiring future clients.

So while I don’t think Intel’s technical abilities should be disrespected like some other people here, I also don’t think there’s much room to be too smug about Intel’s ability to reverse its own technical decline. Intel should have the technical chops to compete, but GlobalFoundries didn’t exit the node shrink game because it was technically incapable of advancing. Unless you have a large government with lots of money backing you and or a captive market where you have no competition for a large pool of clients, there are business questions just as much as there are engineering questions for Intel. (btw this is why Intel really really really wants the CHIPS act to pass).

delete.

siegecrossbow said:

Or maybe they didn’t notice because it wasn’t advertised.

Click to expand...

I'm pretty sure they know. There were a lot of coverage on this, including SMIC's official statements on this. Not likely USG hawks didn't notice.

March 2020- SMIC

"The technology has certain features that are comparable to competing 7 nm process technologies, but SMIC wants to make it clear that N+1 is not a 7 nm technology."

"The foundry from China plans to start risk production using its N+1 technology in Q4 2020, so expect the process to enter high volume manufacturing (HVM) sometimes in 2021 or 2022."


October 2020 - news of N+1 tapeout



Septemer 2021 - more news of N+1

"SMIC's N+1 node has been called 8nm or an early version of the foundry's 7nm process node. Last year the company taped out and tested the N+1 node."

The timing of MinerVA chip that TechInsight analyzed is during timeframe of N+1 production. Multiple sources, including SMIC clearly state it is not 7nm, it's 7nm-like. This is why everyone calls if 8nm and some calls it 10nm. N+2 was not ready last year.


March 2022 - early reporting on SMIC N+2 production

"My analysis shows that SMIC is in production on its N+2 node, equivalent to the 7nm node"

According to our very own @tinrobert , he shard his assessment and news thet N+2 in production. I think he is one of the first to report this. I can confirm that N+2 is in risk production in 2022.

And all of these lead us up to yesterday and the news from TechInsight. SMIC calls the MinerVA 7nm, I think, for a few reasons:
1. technically, N+1/N+2 are both "7nm" family of nodes.
2. to create shock to sale their report.

It's clear from timing of the MinerVA chip production that it is most likely the N+1 variant. I believe with more information from the TechInsight analysis, (someone will buy the report and maybe post it online) the debate whether the bitcoin mining chip is N+1 "8nm" or is N+2 7nm could be settled. Based on info gathered online & those collected from industry sources, I wouldn't bet on this chip being 7nm. In fact, I will go on record to say, the N+1 chip is probably closer to 10nm than 7nm node. Of course, this is my speculation.

At last, yesterday I had shared concern that the US hawks will pounce on this news, I think this is happening. I'm hearing some of my peer companies are already receiving many inquiries from anxious USG officials. Seems like they will make a big deal out of something, this chip, from last year.

latenlazy said:

Whether I agree or not that’s the objective fact. But there’s a reason why serious semis people don’t see Intel’s 10nm as equivalent in performance to TSMC’s 7nm. Trying to shift the attention to density is little more than a bit of Intel marketing speak to salvage Intel’s sliding reputation.

Click to expand...

Oh, I completely agree with you that Intel 10nm (now Intel 7) are now equivalent to tsmc 7nm. I am also aware of tsmc and Intel's open debate about this. Intel was stressing their superior transistor density and tsmc was countering with chip performance.

But as bad as Intel 7 may be in terms of performance metric, people implying it's worse than 10nm node is a bit of a stretch.

latenlazy said:

To be clear I don’t personally hold the view that Intel is incapable of catching up to TSMC. They fell behind because their vertical business model requires a level of fab utilization and wafer utilization efficiency that basically forced them to adopt requirements to preserve density scaling along with node shrinks. The math behind the quantity of chip sales to keep fab upgrades economically worthwhile was brutal, but while Intel was winning with the Wintel monopoly they were able to turn that business model into a finely tuned tick tocking machine. Mobile crowding out PCs really hurt, and really tightened the pressure to keep density scaling apace with the node shrink game (smaller future sales growth, more expensive fab upgrades, less margins to relax utilization efficiencies). But just as ARM was eating away Intel’s future chip sales what really came to a head for them was the physical realities of quantum limitations at smaller feature sizes and FinFET transistor design. Essentially their business model became misaligned from engineering realities. TSMC and Samsung did not have such stringent density requirements, which is one reason they managed to get ahead (though not the only reason). I’ll get to Intel’s 4 nm a bit later.

Click to expand...

I actually have doubts if Intel could catch tsmc by 2025 like they sort of boasted.

latenlazy said:

No. The first order benchmark was always switch speed and switch efficiency. Density was always secondary, but used to be treated as synonymous because all three parameters kept a very tight relationship. That changed with FinFET and with smaller nodes. Today they’re becoming somewhat decoupled. But that’s not just because of 2D node shrinks slowing. The particulars of basic technical parameters have changed post FinFET transition. I think you got the story a bit backward there.

Click to expand...

No. I get you. Performance, Power, Area. We look at all of those. But in general, at least when we compare process nodes and overlay on charts to show technology roadmaps, in general its done with transistor density first. Then we will show supporting charts with other metrics. Perhaps this is a WFE supplier things since physical dimension, independent of performance, do dictate what equipments to purchase/sale and what the patterning/process scheme would be.

latenlazy said:

See above.

My guess, having not checked the technical details, is that Intel 7 is probably roughly equivalent to TSMC 7. But interestingly enough Intel 7 also relaxed its density scaling requirements from Intel 10. Curious!

Click to expand...

"probably equivalent", but like you pointed out earlier, most likely less performance capability than tsmc 7nm despite similar or better density.

latenlazy said:

This is where we get to the prospects for Intel 4. Intel separated its fab and design business to try to shift their business model to better allow it to chase the node shrink and fabrication innovation game. But to do so, they need to be able to find clients who will take on the risk of adopting trial phases of their new nodes in order to subsidize fab development toward mass production for their own chip products. Word on the street right now is that Intel is struggling mightily with the execution details for this part of their new strategy. So while I actually have considerable confidence in Intel’s engineering chops, I am quite a bit more ambivalent about whether the business side of the equation will hold up its end to continue supporting their efforts in the node shrink game.

Why did I bother to go on this long tirade? Because there are some broader implications here for how we think about SMIC’s own efforts. Intel’s ability to continue to push further node shrinks at the same clip as its competition is as much dependent on business questions as it is on engineering ones, and on the business front Intel’s prospects are being challenged significantly by its ability to compete with TSMC for clients. SMIC would be in the *exact* same situation as Intel today, were it not for two very big intervening factors: 1) potentially “wasteful” levels of state support, 2) (imo the far more important factor) a massive captive by default market from the US’s tech bans where SMIC will face almost no competition from acquiring future clients.

Click to expand...

No, this is not a tirade. It's good to have you share your detailed thoughts, so have a better understanding where you are coming from and also finding out a lot of common ground shared. I appreciate this type of sharing, do share and discuss like this more please.

latenlazy said:

So while I don’t think Intel’s technical abilities should be disrespected like some other people here, I also don’t think there’s much room to be too smug about Intel’s ability to reverse its own technical decline.

Click to expand...

Completely agree. Just to be clear, I'm not pro-Intel. But I just thought implying they are not even at 10nm capability is the incorrect perception. They are not good, they have fallen fro grace, but they not THAT bad.

latenlazy said:

Intel should have the technical chops to compete, but GlobalFoundries didn’t exit the node shrink game because it was technically incapable of advancing. Unless you have a large government with lots of money backing you and or a captive market where you have no competition for a large pool of clients, there are business questions just as much as there are engineering questions for Intel. (btw this is why Intel really really really wants the CHIPS act to pass).

Click to expand...

well said.

hvpc said:

I'm pretty sure they know. There were a lot of coverage on this, including SMIC's official statements on this. Not likely USG hawks didn't notice.

March 2020- SMIC

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"The technology has certain features that are comparable to competing 7 nm process technologies, but SMIC wants to make it clear that N+1 is not a 7 nm technology."

"The foundry from China plans to start risk production using its N+1 technology in Q4 2020, so expect the process to enter high volume manufacturing (HVM) sometimes in 2021 or 2022."


October 2020 - news of N+1 tapeout

Please, Log in or Register to view URLs content!

Septemer 2021 - more news of N+1

Please, Log in or Register to view URLs content!

"SMIC's N+1 node has been called 8nm or an early version of the foundry's 7nm process node. Last year the company taped out and tested the N+1 node."

The timing of MinerVA chip that TechInsight analyzed is during timeframe of N+1 production. Multiple sources, including SMIC clearly state it is not 7nm, it's 7nm-like. This is why everyone calls if 8nm and some calls it 10nm. N+2 was not ready last year.


March 2022 - early reporting on SMIC N+2 production

Please, Log in or Register to view URLs content!

"My analysis shows that SMIC is in production on its N+2 node, equivalent to the 7nm node"

According to our very own @tinrobert , he shard his assessment and news thet N+2 in production. I think he is one of the first to report this. I can confirm that N+2 is in risk production in 2022.

And all of these lead us up to yesterday and the news from TechInsight. SMIC calls the MinerVA 7nm, I think, for a few reasons:
1. technically, N+1/N+2 are both "7nm" family of nodes.
2. to create shock to sale their report.

It's clear from timing of the MinerVA chip production that it is most likely the N+1 variant. I believe with more information from the TechInsight analysis, (someone will buy the report and maybe post it online) the debate whether the bitcoin mining chip is N+1 "8nm" or is N+2 7nm could be settled. Based on info gathered online & those collected from industry sources, I wouldn't bet on this chip being 7nm. In fact, I will go on record to say, the N+1 chip is probably closer to 10nm than 7nm node. Of course, this is my speculation.

At last, yesterday I had shared concern that the US hawks will pounce on this news, I think this is happening. I'm hearing some of my peer companies are already receiving many inquiries from anxious USG officials. Seems like they will make a big deal out of something, this chip, from last year.

Click to expand...

Reading all of these comments on the SMIC 7nm, I get the impression that no matter what China does, she will get further sanctioned. seems like if China doesn’t show they have the capability to make advanced chips then the US will sanction them because they feel china has no other options. If China does show capability to manufacture higher node chips, then the US will panic and may use it as an excuse to sanction them.

Since the USG is trying to pounce in this news, what are your suggestions for what China should have done to prevent more sanctions? I personally don’t think there is anything China could have done. The US will always find an excuse to sanction them, no matter how small the reason. I say good for them, they tried to keep a low profile, and while now it is out in the open, irregardless of whether or was planned or not, they will just keep on chugging along. I initially was quite concerned about the sanctions and the trade war. took me a while to see that the sanctions have seriously jump started China’s IC industry, more so than than just pure govt policy could ever have done.

hvpc said:

It's clear from timing of the MinerVA chip production that it is most likely the N+1 variant. I believe with more information from the TechInsight analysis, (someone will buy the report and maybe post it online) the debate whether the bitcoin mining chip is N+1 "8nm" or is N+2 7nm could be settled. Based on info gathered online & those collected from industry sources, I wouldn't bet on this chip being 7nm. In fact, I will go on record to say, the N+1 chip is probably closer to 10nm than 7nm node. Of course, this is my speculation.

Click to expand...

The chip is 7nm (N+2) and produced in 2021 July.

SMIC is now working on 5nm. They must have gotten the most advanced DUVi machines from ASML.