Chinese semiconductor industry

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hvpc

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@FairAndUnbiased & @tokenanalyst , I’m impressed. You guys just don’t cease to amaze. How are you able to have access to so many papers and articles so quickly?

It’s obvious you are both well read. But able to respond so quickly to reference what you had read, find the article, and share with this forum is just incredible.

You must have a very organized hard drive containing all the files.

Amazing!
 

tokenanalyst

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Modern EBL systems have a high depth of focus of several hundred nanometers and can correct for large-scale wafer height variations of several hundred microns. This makes it useful with wafers that have rough surface topology, such as those of gallium nitride (GaN). EBL also allows multiple designs to be fabricated in tandem on one wafer.

However, EBL is a relatively slow and expensive process. This makes it impractical for use in production,
and substrate charging and proximity error effects also need to be accounted for in order to achieve good quality devices, a requirement that adds extra fabrication steps and correction software into the design process.

With the increasing need for early-generation chips with mature nodes, mask-related costs begin to add up. Masks with less demand also have longer lead times, which is a drain on productivity.

According to Multibeam chairman David Lam, MEBL cuts prototyping cost and time because "respins" no longer require a new set of masks. “Since all e-beam columns in our MEBL system write independently and in parallel, they empower production of multi-project wafers and chips larger than the typical optical field of view,” he added.

As a proprietary platform, MEBL can reportedly be applied to ensure “security lithography” by embedding unique security information into each integrated circuit (IC) during wafer fabrication. Multibeam plans to build on this by enabling hardcoding of unique chip IDs into each IC during fabrication, something that would make counterfeiting profoundly more difficult.


even the U.S. says is inefficient and now they are backing the idea of MEBL
 

hvpc

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They do have patents in E-Beam lithography quoting mask production for while and they suggested the method for multi-gate RAD finfets, but i think the process could be really slow for chip development. So i am more inclined to think they could have a low volume ArF immersion lithography machines, Immersion has been in research for quite some time in China.
There is also the wildcard that they are using EUV for low volume chip production, is an Area were China already have some hardware.

Also to be said multiple patterning with Dry lithography could the most credible knowing that we now they have a ArF machine already working.

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View attachment 85547

View attachment 85549
Could you share the entire paper with me? Thanks.
 

FairAndUnbiased

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I only realized after I responded to you that you attached yet another paper. I’m impressed by the fact you seemed to have read a lot of papers and have good understanding of semiconductor process.

So, I quickly glanced through the paper. It was written by someone that most likely do not have actual fab experience. From what I see, he was talking about multiple patterning. Or what is know as LELE (litho-etch-litho-etch). He incorrectly called that double exposure.

Double exposure is LLE. And that is what the previous paper you shared in KrF is.
There's a reason why single photomasks by e beam lithography are like 50k+ even for simple processes. E beam is far more expensive due to the write speed limitation. That's for a single mask set, an IC is even worse.

So for CETC on <45 nm it's either they have an immersion ArF system already, they're using multipatterning dry ArF, or they're using experimental EUV.

Btw, about papers: an expert knows exactly what papers to look for because they know what journals to look in and the key words. Becoming an expert doesn't necessarily mean everything you say is right, it means that you only need a hint to know what is and you know how to get those hints yourself.
 

hvpc

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Modern EBL systems have a high depth of focus of several hundred nanometers and can correct for large-scale wafer height variations of several hundred microns. This makes it useful with wafers that have rough surface topology, such as those of gallium nitride (GaN). EBL also allows multiple designs to be fabricated in tandem on one wafer.

However, EBL is a relatively slow and expensive process. This makes it impractical for use in production,
and substrate charging and proximity error effects also need to be accounted for in order to achieve good quality devices, a requirement that adds extra fabrication steps and correction software into the design process.

With the increasing need for early-generation chips with mature nodes, mask-related costs begin to add up. Masks with less demand also have longer lead times, which is a drain on productivity.

According to Multibeam chairman David Lam, MEBL cuts prototyping cost and time because "respins" no longer require a new set of masks. “Since all e-beam columns in our MEBL system write independently and in parallel, they empower production of multi-project wafers and chips larger than the typical optical field of view,” he added.

As a proprietary platform, MEBL can reportedly be applied to ensure “security lithography” by embedding unique security information into each integrated circuit (IC) during wafer fabrication. Multibeam plans to build on this by enabling hardcoding of unique chip IDs into each IC during fabrication, something that would make counterfeiting profoundly more difficult.


even the U.S. says is inefficient and now they are backing the idea of MEBL

Haha. I interpret this differently than you.

I know about DARPA and Skywaters. This is why I say ebeam for military application would be reasonable. Military application do not need so many chips/wafers so it’s not “production”. And since government are not in the business of profit but more interested in security, ebeam allows to make their own chip without having to rely on civilian fabs. DARPA do outsource some less secure chips, but I would think they make most sensitive chips in house with ebeam.
 

tokenanalyst

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Could you share the entire paper with me? Thanks.
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Is not impossible to get reduced node size but the problem is to reach the performance that is needed, that is why i am not inclined to think is E-Beam, it could be but i am not sure.

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In this paper this researchers archived 32nm in a maskless DMD lithography machine, but i think it could slow for production, even military and i don't know if is posible with a DMD to archive VLSI resolution. It could have applications in photonics, power and other chips.
 

hvpc

Junior Member
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There's a reason why single photomasks by e beam lithography are like 50k+ even for simple processes. E beam is far more expensive due to the write speed limitation. That's for a single mask set, an IC is even worse.

So for CETC on <45 nm it's either they have an immersion ArF system already, they're using multipatterning dry ArF, or they're using experimental EUV.

Btw, about papers: an expert knows exactly what papers to look for because they know what journals to look in and the key words. Becoming an expert doesn't necessarily mean everything you say is right, it means that you only need a hint to know what is and you know how to get those hints yourself.
Come on, man. That’s uncalled for. Was that necessary to take another jab at me?

I never claimed to be an expert. I introduced my background not to boast but to introduce myself so you know what sort of questions you could discuss with me.

Fine, you are the expert. Happy? This is not a competition.

But, all I know is most papers are just that, papers. The difference between academia and industry is, those with actual experience know what papers are full of crap and which has merits. And we don’t need to cite papers….because we have actual knowledge of what’s really going on in the real world.

Like I said, I’m not here to learn about how chips are really made. I’m here for gossips, rumors about the industry. So, I’m sorry for not agreeing with your interpretation of what’s really going on.
 

tokenanalyst

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Haha. I interpret this differently than you.

I know about DARPA and Skywaters. This is why I say ebeam for military application would be reasonable. Military application do not need so many chips/wafers so it’s not “production”. And since government are not in the business of profit but more interested in security, ebeam allows to make their own chip without having to rely on civilian fabs. DARPA do outsource some less secure chips, but I would think they make most sensitive chips in house with ebeam.
So they only used it for very very special applications because how they manage the ultra high density patterns of VLSI applications?

This guys make E-BeamL machines but i dont see VLSI chips in their marketing.

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latenlazy

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Haha. I interpret this differently than you.

I know about DARPA and Skywaters. This is why I say ebeam for military application would be reasonable. Military application do not need so many chips/wafers so it’s not “production”. And since government are not in the business of profit but more interested in security, ebeam allows to make their own chip without having to rely on civilian fabs. DARPA do outsource some less secure chips, but I would think they make most sensitive chips in house with ebeam.
If e-beam for military applications is reasonable because you’re discarding cost efficiency and scale concerns then so is multiple exposure KrF and ArF. Military (and space) applications may not need high scale production, but some scalability is still meaningful, if not for costs, then for time. There is nothing special about using e-beam for military applications. E-beam makes some sense when you’re doing development and prototyping for highly specialized chips (which is what DARPA does, R&D, *not production*), or if you’re designing something for something like a one off satellite, but anything that goes into mass production for military or space equipment makes just as much if not more sense with a photolithograph.
 

FairAndUnbiased

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Come on, man. That’s uncalled for. Was that necessary to take another jab at me?

I never claimed to be an expert. I introduced my background not to boast but to introduce myself so you know what sort of questions you could discuss with me.

Fine, you are the expert. Happy? This is not a competition.

But, all I know is most papers are just that, papers. The difference between academia and industry is, those with actual experience know what papers are full of crap and which has merits. And we don’t need to cite papers….because we have actual knowledge of what’s really going on in the real world.

Like I said, I’m not here to learn about how chips are really made. I’m here for gossips, rumors about the industry. So, I’m sorry for not agreeing with your interpretation of what’s really going on.
I never claimed to be an expert. I'm just completely baffled by your e-beam hypothesis because at typical densities and die sizes you see in VLSI the cost is going to be similar to a photomask set per die i.e. ~20k per die. Whereas multipatterning with dry ArF is, yes, much less efficient. let's say it's 10x more expensive than immersion ArF for similar performance. Still puts you at ~20k per entire wafer.

Yes, true that government doesn't care about cost - but only up to a point. Order of magnitude differences in cost do matter. To my knowledge nobody has made a fully functional VLSI chip via ebeam lithography for any process node even as a one-of. The reality is that a VLSI chip is far too dense. I've seen demonstration devices like a new gate architecture or something made by ebeam, but those are very simple patterns compared to an entire chip.
 
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