None, the value growth mainly comes from DRAM and NAND, which are products in very short supply.
Chinese semiconductor thread II
- Thread starter vincent
- Start date
this boom is mostly related to historic memory prices and Ai
SK hynix Wuxi fab represents about 35% to 40% of its global DRAM output, while Samsung’s Xi'an plant represents roughly 35% to 40% of its global NAND flash capacity. and recently CXMT also started to export some of memory chips but it is still limited.
China's logic chips exports also increase but its modest growth as compare to memory. SMIC says foreign clients shifting orders back to China.
@tamsen_ikard
The vast majority domestic companies.
The South China Morning Post claims that DeepSeek has completed full post-trained training of its latest version v4, a 1.6 trillion-parameter large model, using Huawei's 910C chips.
Huawei chips refine DeepSeek model in major leap for China’s AI self-reliance
While Chinese chipmakers have found success in supporting AI inference, they are struggling with the far more complex process of training
A research team that includes Huawei Technologies says it has successfully used the firm’s Ascend 910C chips to complete post-training for the DeepSeek-V4-Pro model, marking a major step forward as China’s semiconductor industry tries to leap from supporting basic AI inference to more complex model training amid tightening US sanctions. While Chinese chipmakers have found success in supporting AI inference – the relatively simple process of running an already-finished model to answer user prompts – they have struggled with training, the far more complex process of building or refining a model’s brain. If initial “pre-training” teaches a model how to speak by absorbing massive amounts of data, post-training teaches it how to work by following human instructions, safety rules and specific tasks.
To achieve this, the researchers ran DeepSeek’s largest model to date – boasting 1.6 trillion parameters – on a computing cluster powered by at least 1,000 Huawei chips, according to a social media post from the Shenzhen government on Friday.
The team successfully conducted “full-parameter” post-training, meaning the model’s entire architecture was updated and refined without cutting corners, the post said.
Previously, domestic computing power was primarily used for inference, “much like building a one-way road for the model: input a question, output an answer”, the post explained. The project, however, allowed a model to self-reflect and adjust.
This added “complex flyovers and loops to that one-way road, instantly multiplying the computational and communication demands by several times”, it added.
The exploration – jointly conducted by Huawei, the Shenzhen Loop Area Institute, the Shenzhen campus of Harbin Institute of Technology and Shenzhen Research Institute of Big Data – “will help enhance the self-reliance of China’s AI industry chain”, the post said.
Because full pre-training from scratch requires massive infrastructure and months of compute time, many AI teams opt to take open-source models and customise them via post-training instead.
However, the more complicated training processes have historically relied almost entirely on restricted hardware from US chip giants like Nvidia and Advanced Micro Devices, even though Nvidia’s H200 chips were cleared for export by Washington but
When the was launched in April, local chip firms including Huawei, Moore Threads and Cambricon Technologies rushed to announce “day-zero” compatibility for inference.
However, DeepSeek has remained tight-lipped about the hardware stack used to train V4 from scratch. Its predecessor, was trained on a cluster of 2,048 Nvidia H800 processors – chips that are now restricted under US export controls.
The latest trial on Huawei hardware proved both stable and effective, according to the team. The model completed more than 1,500 training iterations without a single interruption or error, while the process also improved the model’s mathematical capabilities, according to an announcement by the Shenzhen Loop Area Institute in May.
While US restrictions on access to advanced chips from American semiconductor giants have slowed Chinese AI model development, they have also forced domestic rivals to try and fill the gap. Some Chinese firms have been experimenting with using domestic chips for model training.
Last month, Baidu executive vice-president Shen Dou said the training of a major version of the firm’s Ernie 5.1 model had been successfully completed on a cluster powered by its Kunlunxin chip unit. But he did not specify which training process its chips were involved in.
In April, Chinese on-demand services group Meituan invited users to test a new trillion-parameter AI model, which local reports said was trained entirely on domestically produced chips.
Meanwhile, Huawei has pushed forward with AI’s agentic capabilities, the ability to perform tasks other than responding to chatbot queries. On Friday, the company’s cloud unit unveiled a new “Agentic Infra” paradigm, which includes new infrastructure such as a platform to allocate compute power for inference and training that can increase resource utilisation by more than 30 per cent.
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CAS team published on Nature Communications of world's first Silicon-graphene-Germanaium (Si-Gr-Ge) barrier transistor that achieved RF testing. It's a vertical 2D base transistor, different than traditional SiGe HBT. Has theoretical limit of > 1 THz, tested with 132 GHz. Needed for 6G base station, high resolution radar, THz imaging + spectroscopy and satellite communications.
Ruijie Innovation: Breakthrough in high-end RF front-end technology across the entire chain
Ruishi has systematically built a full-chain technology ecosystem, successfully developing power amplifiers, RF switches, low-noise amplifiers, and highly integrated modules like DiFEM and L-PAMiD. A cornerstone of its competitive edge is mastering heterogeneous integration the ability to co-design and optimize disparate devices within ultra-compact spaces while mitigating electromagnetic interference, thermal crosstalk, and parasitic effects. The company has also pioneered advanced packaging solutions, including a proprietary 3D printing cavity formation technology for filters. This innovation significantly reduces material costs, overcomes traditional spacing limitations, enables more compact component layouts, and accelerates production efficiency compared to conventional wafer-level packaging methods.
Central to Ruishi’s strategic advantage is its focus on filter capabilities, guided by the industry principle that "one generation of modules requires one generation of filters." Recognizing that high-end MEMS filter performance depends heavily on manufacturing processes rather than design alone, the company adopted a "Fab-lite" model to internalize core production. This end-to-end control enables rapid co-iteration between filter fabrication and module architecture, ensures supply chain resilience amid global trade volatility, and creates a deep, difficult-to-replicate technological moat that traditional fabless models cannot match.
Beyond its own product advancements, Ruishi is acting as an industrial catalyst by driving upstream ecosystem localization. Through large-scale commercial orders and forward-looking technical collaboration, the company has accelerated the validation and iterative upgrade of domestic materials and process platforms, including advanced SOI/POI substrates and Huahong’s RF-SOI processes. This demand-driven innovation model is shifting China’s semiconductor supply chain from fragile dependency to resilient self-reliance. Bolstered by a robust patent portfolio that ranks first domestically and second globally in RF front-end technologies, Ruishi is no longer merely competing on performance metrics but is actively participating in shaping next-generation standards, securing its position at the commanding heights of the global RF industry.
Domestic RF front-end manufacturers have achieved a high market share in the low-to-mid-end product sector and gradually breaking into the high-end market. Against this backdrop, filter capabilities have become a crucial foundation for companies to penetrate the high-end market. In recent years, leading companies in the industry have accelerated their layout in the filter field: Ruijie Microelectronics and Zhuosheng Microelectronics have established their own filter production lines; Onsemi Microelectronics has strengthened its R&D by building a filter R&D experimental line; and Vanchip recently announced its plan to acquire a 33.4% stake in Sibaike to supplement its filter design capabilities. The fact that major companies in the industry are all extending into the filter segment reflects that "module + filter" collaborative innovation has become an important trend in the development of the RF front-end industry, and mastering filter capabilities is gradually becoming key for companies to gain competitiveness in the high-end market and product definition rights.
Breakthrough in key materials for 2.5D/3D packaging: Aisen launches ultra-thick film positive chemical amplification photoresist.
Aisen has over 10 years of development history in RDL/Fine-pitch RDL applications, and has launched multiple series of products including positive, negative, and chemically amplified photoresists. Among them, the iCA 7200 series chemically amplified positive photoresists can achieve a linewidth/pitch of <2μm and an aspect ratio (AR) of over 5:1 at a film thickness of 6μm, meeting the needs of high-density interconnects.
In the field of bump/micro-bump technology, the company's 5060N and 5090N series of thick-film negative photoresists have been widely used in Cu/Ni/SnAg electroplating processes. The 5090N series maintains a 5:1 aspect ratio even at film thicknesses of 250~300μm. For gold bump processes, the 5025N series also exhibits excellent gold plating tolerance. To further meet the requirements of higher integration, Aisen Technology is developing a new generation of products with an aspect ratio of 7:1 and a resolution of 5μm via a film thickness of 35μm.
In the field of positive chemical amplification photoresists for micro-bump applications, the CA7150 series achieves 10-15μm openings with an AR ratio exceeding 5:1 at film thicknesses of 50-80μm. The company has successfully solved the problems of photo-acid quenching reaction on copper substrates and bubble formation during coating and baking by optimizing resin structure and formulation. It is currently developing ultra-thick positive chemical amplification photoresists supporting film thicknesses from 110μm (single coating) to 250μm (two coatings).
For TSV applications, Aisen Technology is developing the ICA7110 positive chemical amplification photoresist, suitable for <2μm via @8~12μm film thickness. It features high vertical morphology and excellent resistance to fluorine-containing etching gases, supports -15℃, 30-minute DRIE process, and achieves an AR ratio of 5~6:1. Furthermore, the iCA7200, ICA7110, and CA7150 product combination provides complete photoresist material support for 2.5D/3D packaging structures such as silicon interposers, partial silicon interconnects, and embedded bridging interconnects.
In the field of dielectric and buffer protective layers, Aisen has completed the full range of PSPI products, covering high-temperature curing (~350℃), low-temperature curing (200~250℃), and ultra-low-temperature curing (180~200℃) products, and has developed low dielectric constant (Dk/Df) materials to meet the needs of high-frequency applications. Some products are innovative developments to meet new customer needs, and there are currently no comparable products on the market.
Xiang Wensheng emphasized that Aisen Technology adheres to its dual-main-business strategy of "electroplating + lithography," continuously focusing on advanced node logic and memory, advanced packaging, and specialized application areas such as power/RF/display/sensing. The company has multiple R&D and production bases in Kunshan, Guangzhou, Nantong, and other locations, and successfully listed on the STAR Market in December 2023
HGLaser Accelerates Mass Production of Glass Substrates with Advanced TGV Laser Drilling Equipment
Driven by surging demand for AI chips, CPO optical modules, and RF MEMS, the semiconductor industry is shifting from traditional organic substrates to glass substrates due to their superior high-frequency performance, dimensional stability, and interconnect density. The key hurdle has been Through-Glass Via (TGV) drilling, which requires micron-level precision at scale. HGLaser has overcome this bottleneck with its intelligent laser processing system, leveraging proprietary Rapid Beam Deflection and Synchronous Positioning Technology to achieve 5,000–8,000 holes per second (up to 8,000 max), representing a 5–8× efficiency leap over industry averages. The equipment delivers 5μm hole diameters, 1:100 aspect ratios, and a 99.9% through-hole success rate. With core components fully domestically produced and pilot verification completed, the system is now ready for large-scale deployment in advanced packaging (2.5D/3D AI chips, CPO optical engines, RF/MEMS), effectively transforming TGV technology into scalable industrial capability.
