Chinese semiconductor thread II

[tokenanalyst]

Single pass overlay accuracy is not the same thing as overlay error stack from multiple passes.

That is why they put matched machine overlay to take into account different layers between different machines because these systems are built for multiple patterning. For the NXT:2150i is almost 1nm between multiple layers.

The issue with trying to replicate each EUV patterning steps with 2-4 more patterning steps using DUVi is about error stack from multiple pass throughs, not about the inherent accuracy of the instrument itself. This is pretty fundamental to the point I’ve been trying to raise.

At the end of the day is about the pattern that you want to process and how much it cost you. DUVi is more mature, the machines cost less and the materials cost less. I think for a 7nm node cost is similar for LowNA EUV and DUVi. The cost of Low NA EUV increase significantly as you get into MP. The throughput is lower, the machine cost more, EUV defects issues and the processing cost more. But that will no be forever. Throughput is getting higher, the supply chain is maturing and the ownership cost is stabilizing.

 

[interestedseal]

interesting if true. Huawei slowly and steadily getting into chip manufacturing so this was expected outcome.

@jx191

Rumor is highly credible since HW officially confirmed their proprietary HBM called HiZQ2.0. In fact the performance (144 GB 4TB) closely matches HBM3e

 

[latenlazy]

That is why they put matched machine overlay to take into account different layers between different machines because these systems are built for multiple patterning.

While such practices can help they also don’t remove the fundamental statistical mechanics behind error stacking issues. You can reduce error stack from multiple pass throughs with quality control measures but you can’t eliminate the fundamental dynamic that those errors multiply with each additional step. Process control based error mitigation also apply equally to both EUV and DUVi, so the relative difference in error stacking multipliers is invariant for between instrument comparisons. It’s always going to be fundamentally tied to the number of patterning steps you employ.

At the end of the day is about the pattern that you want to process and how much it cost you. DUVi is more mature, the machines cost less and the materials cost less. I think for a 7nm node cost is similar for LowNA EUV and DUVi. The cost of Low NA EUV increase significantly as you get into MP. The throughput is lower, the machine cost more, EUV defects issues and the processing cost more. But that will no be forever. Throughput is getting higher, the supply chain is maturing and the ownership cost is stabilizing.

Of course it depends on the details of the specific patterning step, but the point remains that there are critical patterning steps that come from higher resolution and tighter error tolerance requirements where DUVi cannot adequately substitute EUV, which tells you that the performance difference in technical terms is not modest and is not drowned out by the other pain points of an EUV process.

 

[tokenanalyst]

Of course it depends on the details of the specific patterning step, but the point remains that there are critical patterning steps that come from higher resolution and lower error tolerance requirements where DUVi cannot adequately substitute EUV, which tells you that the performance difference in technical terms is not modest.

There are a lot of "cheap" "cost effective" RET for immersion OPC, phase mask shift, off axis illumination, Self Alignment, MP and so that. Yes, mastering those is basically semiconductor kung fu but achievable. As long you matched overlay metrology is good, you are ok,

In LowNA EUV the resolvable resolution is theoretically 14nm but that is not what fabs are getting, because stochastics they have to go into multiple patterning and that rise their costs because the throughput of these systems in pretty low for now. That is why the pressure for High NA EUV. HighNA is suppose to solve those problems.

But TSMC is "betting" that the technology will mature and the NXE throughput is going to get higher, if you go to the patent literature they are developing number of RET for EUV. It could be that TSMC is doing the right decision to wait.

I think because the AI boom fabs are passing the EUV learning cost to the consumers because AI companies will pay whatever for these chips and only going to get worse with the arrival of HiNA EUV.

 

[latenlazy]

In LowNA EUV the resolvable resolution is theoretically 14nm but that is not what fabs are getting, because stochastics they have to go into multiple patterning and that rise their costs because the throughput of these systems in pretty low for now. That is why the pressure for High NA EUV. HighNA is suppose to solve those problems.

You’re missing the point. If the stochastics were overwhelming the resolution advantage then steps employing EUV would have already been swapped for DUVi wholesale. It’s been almost a decade since low NA EUV first entered adoption. That they haven’t wholesale swapped to DUVi despite these now very well known issues especially after adding how many new advanced node lines since initial EUV adoption tells you that there are some patterning steps where adding more passes with DUVi is too performance limiting and not in fact making up the difference with an EUV process. Commercial decisions are based on practical cost benefit assessments driven by revenue imperatives.

 

[tokenanalyst]

You’re missing the point. If the stochastics were overwhelming the resolution advantage then steps employing EUV would have already been swapped for DUVi wholesale. It’s been almost a decade since low NA EUV first entered adoption.

EUV adoption didn´t happen overnight, was a learning curve. Intel first, then TSMC, then Samsung and finally the RAM makers.

That they haven’t wholesale swapped to DUVi despite these now very well known issues especially after adding how many new advanced node lines since initial EUV adoption tells you that there are some patterning steps where adding more passes with DUVi is too performance limiting and not in fact making up the difference with an EUV process. Commercial decisions are based on practical cost benefit assessments driven by revenue imperatives.

I already stated the reason why EUV was adopted and goes beyond performance, in fact the NXE:3400A, NXE:3400B had horrible performance compared to a NXT:2050i (125WPH vs 295WPH) . Both are marketed for 7m and 5nm process nodes, the NXT:2050 was simple a bit more cost effective in critical layers using SAQP than Low NA EUV DP 7nm or TP or QP? 5nm. Why was adopted? my guess is that allowed fabs to overcome the learning curve sooner. Now the NXE:3400E boast 220WPH and the overlay closer to the NXT:2150i so the math is starting to favor Low NA EUV and even better with High NA EUV boasting 175 WPH and 8nm resolution allowing SP again

 

[tokenanalyst]

Huawei Hubble and others invest in Miltech, aiming to tackle the field of indium phosphide photonics chips.​

According to Tianyancha App, Mier Optoelectronics (Beijing) Co., Ltd. recently underwent an industrial and commercial registration change, adding Huawei's Shenzhen Hubble Technology Investment Partnership (Limited Partnership) and others as shareholders. The company's registered capital increased from approximately RMB 5.155 million to approximately RMB 5.514 million, marking the successful completion of its angel round financing.

According to a statement on the official website of Mier Optoelectronics, this round of angel round financing will be mainly used for the company's product research and development iteration and core team building, further accelerating the company's layout in core optoelectronic devices for next-generation all-photon wireless technology.

It is understood that Mildred Semiconductor was established in 2021, focusing on indium phosphide-based high-speed optical chips. Its core product is a single-carrier photodetector, which is mainly used in 800G/1.6T high-speed optical modules, 6G all-photon wireless base stations and high-speed interconnection of AI data centers. Its long-term goal is to break the overseas monopoly in the fields of indium phosphide materials and high-speed optical chips.​

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[latenlazy]

I already stated the reason why EUV was adopted and goes beyond performance, in fact the NXE:3400A, NXE:3400B had horrible performance compared to a NXT:2050i (125WPH vs 295WPH) . Both are marketed for 7m and 5nm process nodes, the NXT:2050 was simple a bit more cost effective in critical layers using SAQP than Low NA EUV DP 7nm or TP or QP? 5nm. Why was adopted? my guess is that allowed fabs to overcome the learning curve sooner. Now the NXE:3400E boast 220WPH and the overlay closer to the NXT:2150i so the math is starting to favor Low NA EUV and even better with High NA EUV boasting 175 WPH and 8nm resolution allowing SP again

WPH is not the only parameter that matters. Having higher WPH but also requiring more steps that increase your defect rates for the same intended final pattern is not a categorical win. Your guess is pretending that there aren’t other technical considerations outside of wafer processing speed.

 

[FriedButter]

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Ex-Samsung Chip Boss Says China’s DRAM Blitz Could Crush The 414% DDR5 Price Spike Within A Year​

With the memory chip market being significantly disrupted due to high demand from the artificial intelligence market, advisor to Samsung Electronics, Kye-hyun Kyung, believes that prices will come down in the second half of next year. Kyung previously served as the head of Samsung's Device Solutions (DS) group, which is the firm's chip and display manufacturing business division.

The former executive believes that high investment by China in the memory market will be responsible for the lower prices and adds that Korea needs to expand its presence in the global fabless chip fabrication market in order to remain competitive with the US and China.

Aggressive Chinese Production Capacity Expansion Could Lead To Memory Supply Surge, Says Former Samsung Executive

The booming demand for AI chips and the key role played by high-bandwidth memory (HBM) in it have led to a surge in global memory prices. Even though the highest-performing AI chips require HBM, the market shortage has also affected prices for other memory chips, such as DDR5, due to reallocation of production capacity.

For instance, as of May, memory prices in Germany are up by a whopping 414% for DDR5 chips compared to the prices from July 2025. The high prices have also affected the personal computing market with companies such as Apple and Dell experiencing a jump in shipments due to preemptive ordering ahead of the high prices' impact on the market.

Memory Production Capacity Investments Depend On Mega Cap CapEX Returns, Warns Former Executive

Amidst this turmoil, the former head of Samsung's DS Group, Kye-hyun Kyung, believes that memory prices can fall starting from the second half of next year. Speaking at the 285th National Academy of Engineering of Korea (NAEK) Forum, the former executive remarked that Chinese companies are investing aggressively to boost their memory chip production.

According to him, if these investments are successful and lead to an increase in output, then the surge in supply could cause prices to fall a year from now in the second half of next year.

Kyung's remarks come as Chinese firms start to increase their presence in the DDR5 market. The largest player in the Chinese DRAM market, ChangXin Memory Technologies (CXMT), is believed to be leading the charge. Other players, such as Jiahe Jinwei, are also making an impact.

Kyung cited data from market research firms to point out that production capacity in H2 2027 could sit at six million wafers per month. However, he cautioned that the production investments could drop if mega technology firms see their return on investment on AI capital expenditure drop.

Kyung cited data from market research firms to point out that production capacity in H2 2027 could sit at six million wafers per month

 

[pbd456]

WPH is not the only parameter that matters. Having higher WPH but also requiring more steps that increase your defect rates for the same intended final pattern is not a categorical win. Your guess is pretending that there aren’t other technical considerations outside of wafer processing speed.

Defect rate is not static and it decreases over time as the process is matured with prior skills.