Chinese semiconductor thread II

tphuang

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My read on the B30A situation. Clearly, you cannot have access to better US chips until domestic alternative is available and real.

And Tencent comment on H20 pretty much has killed Nvidia's hope of capitalizing on their stock of H20s. No way ByteDance and Alibaba will be able to buy H20 after that.
 

Hyper

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My read on the B30A situation. Clearly, you cannot have access to better US chips until domestic alternative is available and real.

And Tencent comment on H20 pretty much has killed Nvidia's hope of capitalizing on their stock of H20s. No way ByteDance and Alibaba will be able to buy H20 after that.
Who says they don't have access to blackwell. They probably do have access to it.
 

tokenanalyst

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AI+EDA ignites the Fab Revolution: HuaDa Empyrean Vision Tool Takes the Lead in the Yield War​


Global foundry market revenue is projected to reach $169.8 billion by 2025 (IC Insights). Yield is the absolute lifeline for fab profitability. For memory fabs, a 1% yield improvement = $110 million annual net profit; for cutting-edge logic fabs, it equals $150 million. This value escalates as processes advance: 3nm 12-inch wafers now cost $20,000 (25% higher than 5nm wafers, TrendForce). Manual inspection requires inspectors to examine every wafer microstructure via microscopes (time-intensive, subjective). Rule-based algorithms: Fail to detect new defect types due to rigid predefined rules and poor handling of data coupling. Core problem: Yield hinges on coupled variables across the entire process chain (e.g., silicon purity, photolithography alignment errors, etching temperature deviations, film thickness uniformity). As process complexity grows, variable count and coupling intensify, making traditional diagnostics obsolete.

HuaDa Empyrean Vision’s AI-Driven Breakthrough:

Vision HP (Intelligent Risk Prediction) Plataform:

Analyzes only 2% of the chip’s critical area to identify >16,000 unique risk points.
100x higher defect capture rate vs. traditional methods.

Vision ID (Generative Outline Prediction - Offline Intelligent Measurement Revolution):
Generates actual silicon wafer outline directly from design layout to "design-by-prediction."
Provides one-stop support for images from NGR, HVSEM, CD-SEM, and E-beam equipment without occupying machine resources.

Vision PD (Intelligent Defect Analysis):
Integrates design attributes + defect characteristics to automatically identify defects and pinpoint root causes (eliminating subjective omissions).

The Vision platform seamlessly connects Design → Mask → Wafer → Product. This solves data fragmentation and one-sided analysis—the core weakness of legacy EDA tools—making yield improvement "clearly visible" via EDA + AI.

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tokenanalyst

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Moore's Law: New Server GPU S3000E Coming Soon

Recently, media reported that the GPU information software GPU-Z has added support for Moore's Law S3000E GPU in its latest released version v2.68.0. This means that Moore's Thread is expected to launch a new server GPU, model named S3000E, which may be a low-power version of the existing S3000 model. The Moore's Law S3000 was released in 2022 and is equipped with 4096 MUSA cores, running at a frequency of 1.9 GHz, and equipped with 256-bit 32GB GDDR6 video memory.

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Moore Thread, founded in 2020, is a high-tech integrated circuit company specializing in full-featured GPU chip design. In June of this year, Moore Thread submitted an IPO application for listing on the Science and Technology Innovation Board (STAR Market), aiming to raise 8 billion yuan. The application was accepted by the Shanghai Stock Exchange on July 1, 2025.

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tokenanalyst

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Changan DeepBlue & Star: SiC project put into production, with production capacity reaching 1.8 million wafers.​


according to DeepBlue Auto's official Weibo account, the Chongqing Anda Semiconductor Project, a joint venture between DeepBlue Auto and Star Semiconductor, was officially put into production recently.DeepBlue Automotive further revealed that through its joint venture, they are developing industry-leading automotive-grade power semiconductors, setting a new benchmark in the industry. In the future, they will develop next-generation PCB-embedded SiC power modules, providing core modules for high-performance electric drives, significantly improving system current output capabilities and maintaining their industry-leading position.According to a previous report by "Experts Talking about Three and a Half Generations", the Chongqing Anda Silicon Carbide Project began in 2023 and was put into production in just about two years:​
  • In May 2023, the project was signed and settled in Western (Chongqing) Science City, with investment in the construction of an automotive-grade module production base, and plans to realize the research and development, production and sales of high-power automotive-grade IGBT modules and automotive-grade silicon carbide modules for main controllers.​
  • In March 2025, Anda Semiconductor officials revealed that the project had officially topped out, with equipment expected to be ready by May of this year and small-batch production to begin in June. Furthermore, the production line will be built to Industry 4.0 standards, with virtually unmanned operation. The first phase will have a production capacity of 500,000 wafers, and the second phase will reach 1.8 million wafers.
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tokenanalyst

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Optimizing Monolithic CFET Middle-of-Line Contact Architectures at A10 Node (1.X nm?): A DTCO Simulation Study.​

Abstract:
As transistor scaling approaches physical limits, monolithic complementary field-effect transistors (CFETs) offer a promising path forward but suffer from critical parasitic challenges in middle-of-line (MOL) interconnects. We propose a semi-wrap-around contact (Semi-WAC) scheme that simultaneously mitigates parasitic resistance and enables cell height scaling. Here, we systematically optimize MOL contact architectures through design-technology co-optimization (DTCO), evaluating top contact (TC), wrap-around contact (WAC), and Semi-WAC schemes with single-, dual-, and triple-nanosheet stacks, respectively. Through 3-D TCAD and SPICE simulations, Semi-WAC significantly reduces parasitic resistance at three-stacked nanosheet CFETs (NNS=3), increasing ON-current 9.1%. By further integrating gate spacer dielectric constant (k = 3.0) to suppress parasitic capacitance, Semi-WAC resolves the inherent RC tradeoff of wraparound contacts, achieving 8.5% higher maximum frequency fmax and 11.3% lower dynamic power. This demonstrates Semi-WAC with low-k spacer optimization as a scalable solution for next-generation CFETs.​

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tokenanalyst

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Based on STCO integrated system design to expand the ecosystem, Core Semiconductor and Kylin Software have completed the operating system level​


Coreplus Semiconductor Technology (Shanghai) Co., Ltd. ("Coreplus Semiconductor") and KylinSoft Co., Ltd. ("KylinSoft") recently announced that they have completed mutual product compatibility certification. Coreplus Semiconductor's diverse "chip-to-system" multiphysics simulation and system verification EDA products now run efficiently and stably on the Kylin Advanced Server Operating System (Industrial Edition) V10, marking the successful expansion of Coreplus Semiconductor's "STCO Integrated System Design" philosophy into the operating system layer.

By 2025, the information and innovation industry will enter a period of comprehensive development. According to CCID data, the penetration rate of domestic EDA has been less than 10% in the past two years, and over 85% of high-end manufacturing companies face the risk of overseas tool supply disruptions. The science and technology industry planning during the 15th Five-Year Plan period has elevated industrial software autonomy to a strategic level.

As a domestic expert in integrated system design EDA, Xinhe Semiconductor has seized the important development opportunities of domestic EDA companies and has carried out in-depth collaborative cooperation with Kylin Software. This mutual certification covers Xinhe Semiconductor's five key EDA platforms:
  • Metis, a 2.5D/3D advanced packaging SI/PI simulation platform, addresses the complex electromagnetic coupling issues brought about by interposer high-density interconnection and TSV vertical integration, providing full-link electromagnetic field rapid simulation and high-precision model extraction capabilities.​
  • Notus, a board-level multi-field collaborative simulation platform, provides SI/PI collaborative analysis, topology extraction, and electrical-thermal-stress joint analysis at the package and board levels in high-speed, high-frequency design. It can quickly analyze signal, power, temperature, and stress distribution, accelerating user design iterations.​
  • ChannelExpert, a high-speed system verification platform, provides a universal verification platform for high-speed channel signals across the entire signal integrity chain, encompassing both time and frequency domains. This platform enables fast, accurate, and easy evaluation, analysis, and resolution of high-speed channel signal integrity issues.​
  • Hermes3D, a three-dimensional full-wave electromagnetic simulation platform, provides extraction of package board-level signal models, electromagnetic simulation of arbitrary three-dimensional structures, RLGC parameter extraction, and board-level antenna simulation.​
  • RF EDA Design Platform XDS: This RF system design platform targets chip-package-module-PCB, supports a PDK-driven field-circuit co-simulation process, and embeds a 3D full-wave fast electromagnetic simulation engine based on the method of moments and finite elements, supporting cross-scale simulation from chip to package.​
The above-mentioned Xinhe Semiconductor EDA platforms have all completed the Kylin Advanced Server Operating System (Industrial Edition) V10 certification, covering the mainstream design needs in China from chips to packaging to systems, and meeting the urgent needs of enterprises in data centers, communication base stations, automotive electronics, smart terminals, industrial equipment, new energy, Internet of Things and other fields for full-chain independent control.

This mutual certification is a significant example of collaborative innovation in domestic industrial software. Xinhe Semiconductor, leveraging the Kylin operating system, has achieved localized deployment of key EDA components, helping high-end design and manufacturing companies reduce their reliance on overseas EDA tools. Kylin Software, in turn, has further strengthened its support capabilities for the industrial application ecosystem. Going forward, both parties will continue to deepen their technological research, helping more companies shorten R&D cycles and improve innovation efficiency. This will drive the full autonomy of the "chip-EDA-OS-application" chain, providing the underlying technical support for the intelligent upgrade of China's manufacturing industry.​


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Wrought

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Nikkei claims local targets towards domestic chips exceed the previously reported threshold of 50%. Plausible enough, given the way central gov mandates trickle down to the provinces.

A Shanghai municipal government plan calls for China to be able to exercise independent control over 70% of the semiconductors used in data centers. The ratio is said to refer to semiconductors designed or manufactured by Chinese companies.

In Beijing, where many central government agencies are located, the municipality adopted a plan to increase the self-sufficiency ratio to 100% by 2027.

The inland city of Guiyang has requested that about 90% of the semiconductors used in data centers currently under construction be made in China. Guiyang is home to a large concentration of data centers, such as the one used by Apple.

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Directly related to the above, domestic production continues to reach record highs.

 
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