Chinese semiconductor thread II
- Thread starter vincent
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Xi'an Yicai's monthly production and sales of 12-inch silicon wafers exceeded one million pieces; construction of its Wuhan base accelerated.
Xi'an Yicai issued a voluntary information disclosure announcement. The announcement showed that in June 2026, the company's monthly production and sales of 12-inch electronic-grade silicon wafers exceeded 1 million pieces, setting a new record for large-scale supply capacity. This achievement stemmed from the continued progress of the company's second factory capacity expansion project.
The company's medium- and long-term capacity expansion is progressing simultaneously. The main structure of the factory building at the company's Wuhan production base was completed in May 2026, and construction of supporting facilities such as cleanrooms, electromechanical systems, and fire protection is currently underway. According to the project schedule, the base is expected to begin equipment installation ahead of schedule in October 2026 and achieve initial production capacity in the first half of 2027.
According to the plan, once all three factories currently under construction are fully operational, the company's total 12-inch electronic-grade silicon wafer production capacity will exceed 1.8 million wafers per month.
Public information shows that Xi'an Yicai mainly engages in the R&D, production and sales of 12-inch electronic-grade silicon wafers, with products targeting logic chips, memory, image sensors and other fields. It is a core supplier of 12-inch silicon wafers in China. As a core substrate for wafer manufacturing, the demand for 12-inch silicon wafers continues to grow steadily downstream, driven by mature processes and the recovery in demand for AI-related chips.
If SMIC can get the overlay budget in control, I think is possible to SMIC to develop ICs based on gate around transistors.
Gazer GPU based millisecond SiC epitaxial measurements
A critical, often overlooked bottleneck: Silicon Carbide (SiC) power devices underpinning new energy vehicles, photovoltaics, and high-voltage power grids. For SiC MOSFETs, the thickness precision of the epitaxial layer—situated between the substrate and the drift layer—directly determines the device's voltage-withstanding capability. High-end 4H-SiC wafers feature 5–8 doped epitaxial layers with a total thickness of 1–20 micrometers (merely 1/500th the thickness of a human hair). Traditional FTIR spectroscopic inspection relies on CPU-based calculations to solve the inverse problem for multi-layer films; a single computation takes hundreds of milliseconds, directly slowing down the production line's cycle time. FTIR (Fourier Transform Infrared) interferometry: Thickness precision is the critical factor determining device voltage ratings and on-resistance.
Homodyne Littrow grating interferometer for two-degrees-of-freedom measurement
Abstract:
In response to the current demand for high-precision planar displacement measurements in advanced manufacturing equipment, this paper proposes an xz dual-axis grating interferometer. The system adopts a biaxial Littrow incident light path structure, established using a biaxial beam splitter mirror and right angled prism mirror. The relationship between the parallelism of the outgoing beam, the beam spacing, and the position and angle of the incident light is analyzed. Experimental results verify the feasibility and measurement performance of the proposed interferometer. The grating interferometer achieves a displacement resolution of 4 nm along the x-axis and 7nm along the z-axis. After correction using the Heydemann algorithm, the periodic nonlinear error is reduced to ±5 nm. Over a travel range of 10 mm, the measurement accuracies are ±30 nm along the x-axis and ±100 nm along the z-axis, respectively. Finally, the influence of the surface error introduced by the non-coincident incident structure on the measurement results is discussed.
I wrote here about the usage of hybrid bonding and other forms of 3D stacking of DRAMs on logic die/wafer to improve AI inference chip/node performance and what this is allowing Chinese AI industries to achieve.