The Natural Science Foundation of China released the 2024 Project Guidelines for the Scientific Basics Major Research Plan on Frontier Technology of Integrated Chips, with a maximum of 15 million yuan per project.
2. Core scientific issues
This major research plan focuses on the problems of decomposition, combination and integration of integrated chips after the number and types of core particles have been greatly increased, and focuses on the following three core scientific issues:
(1) Mathematical description and combinatorial optimization theory of core particles.
Explore the abstract mathematical description method of integrated chips and core particles, and construct the mapping, simulation and optimization theory of complex functions from integrated chips to core particles.
(2) Large-scale chip parallel architecture and design automation.
Explore the integrated chip design methodology after the chip integration level has been greatly improved, study multi-core interconnection architecture and circuits, layout and routing methods, etc., to support the design of hundred-core/ten thousand-core scale integrated chips.
(3) Multi-physics coupling mechanism and interface theory at the core particle scale.
Clarify the mutual coupling mechanism of electric-thermal-force multi-physics in integrated chips under the three-dimensional structure, build a fast and accurate simulation calculation method for multi-physics and multi-interface coupling at the core particle scale, and support the design and manufacturing of 3D integrated chips.
(1) Cultivation projects.
Based on the above scientific issues and driven by the overall scientific goals, in 2024, it is planned to give priority to funding application projects that are exploratory, have original ideas, and propose new technological paths around the following research directions:
1. Core particle decomposition and reusable design method.
Research the formal description of integrated chips and core particles, decomposition-combination theory and modeling methods, and study reusable design methods of core particles such as computing/storage/interconnection/power/sensing/radio frequency.
2. Multi-core parallel processing and interconnection architecture.
Research on high computing power and scalable architecture for 2.5D/3D integration, interconnection networks and fault-tolerance mechanisms between cores such as computing/storage/communication, multi-core heterogeneous compilation tool chains, etc.
3. Integrated chip multi-field simulation and EDA.
Research on electro-thermal-mechanical coupling multi-physics calculation methods and rapid simulation tools for the core particle scale, integrated/layout/wiring automated design tools for integrated chips, testability design of integrated chips, etc.
4. Integrated chip circuit design technology.
Research on high-speed, energy-efficient serial/parallel, radio frequency/wireless, silicon optical interface circuits for 2.5D/3D integration, power management circuits and systems for high-power integrated chips, etc.
5. Integrated chip 2.5D/3D process technology.
Research the manufacturing technology of large-size silicon substrates (Interposer), high-density and highly reliable 2.5D/3D integration processes and materials, heat dissipation methods for 10,000-watt chips, optoelectronic integrated packaging processes, etc.
(2) Key support projects.
Based on the core scientific issues of this major research plan and driven by the overall scientific goal, in 2024, it is planned to give priority to funding application projects with good accumulation of early research results, strong cross-cutting, and greater contributions to the overall scientific goal:
1. Cache coherence and storage systems.
Study the cache coherence mechanism of heterogeneous multi-core systems, explore the multi-level cache architecture of integrated chips, scalable storage management mechanisms, and on-chip network-based memory access optimization strategies and quality of service (QoS) optimization mechanisms. Construct a behavior-level model of cache consistency between cores, supporting cache consistency between ≥ 2 types of heterogeneous cores (CPU, GPU, etc.), the total number of CPU cores ≥ 256, and the stable state of ≥ 7 cache lines. Typical latency is <200 cycles, and an open source functional verification simulator is available.
2. Core particle decomposition and combination optimization method.
For computing scenarios such as end-edge-cloud, study core particle decomposition and combination optimization theory, explore the functional representation of core particles, establish mapping of complex applications to core particles, study the stability and robustness of mapping theory, and form a complete Core particle library construction method.
3. Layout and wiring method of multi-reticle integrated chip.
With the goal of minimizing the number of mask layers and cross-mask interconnections in silicon substrate manufacturing, study the automated layout and wiring method of multi-mask integrated chips, and explore the TSV/interconnect line/deep trench capacitor process and design collaborative optimization method.
4. Testability design method for integrated chips.
Research the integrated chip test bus architecture with high testability, plug-and-play and low overhead, break through the bottleneck caused by limited observable pins, explore hierarchical test scheduling and fault diagnosis technologies for integrated chips, and achieve testability Design EDA tools and open source them, with interconnection fault coverage ≥99% and test architecture hardware overhead ≤5%.
5. Energy-efficient chip-to-chip interconnect single-ended parallel interface circuit.
Research high-energy-efficiency, high-density 2.5D parallel interconnect interface circuit technology.
6. Multi-field simulation algorithm and solver for core particle scale .
Research the electro-thermal-mechanical coupling model for the core particle integration process, explore the multi-physics simulation numerical method of the key structure, materials and interfaces of the integrated chip, realize automatic calculation grid division, develop a cross-scale multi-field simulation solver and Open source, the error range of calculation accuracy and experimental results is less than 10%.
7. Large-size silicon substrate manufacturing technology and warpage model and stress optimization.
Research large-size silicon substrate (Interposer) manufacturing technology, build wafer-level warpage models and stress optimization methods, and explore the stress of high-density, high-aspect-ratio through-silicon vias (TSV), deep trench capacitors (DTC) and other manufacturing processes .
8. Three-dimensional integration of efficient heat dissipation materials and structures.
Explore the heat distribution characteristics and efficient heat transport mechanism under strong coupling of multiple hot spots, the integration of new heterogeneous heat dissipation materials and interface heat transport control methods, the structural design of micro-channel radiators and enhanced heat transfer methods.
(3) Integration projects.
This year, it is planned to select research directions with significant application value and good research foundation for integrated funding. The specific research directions are as follows:
1. Heterogeneous computing three-dimensional integrated chip.
Research cross-level collaborative design methods for three-dimensional integrated chips, explore modular combination and optimization methods of heterogeneous cores, and verify key technologies such as vertical power supply architecture and circuits, automated silicon substrate layout and wiring, and high-density core-wafer bonding.
