You only think I'm a good teacher because I'm not saying anything in enough detail to fly over your head. That's because I am not an expert. Actual experts are the ones in the industry and those writing research papers.
We should remind ourselves that most research never makes it out of the lab. However, these architectures appear so compelling that it would be stupid not to pursue them commercially. It's like SSMB, it would be stupid for China not to pursue it. From what little I know about these 2 architectures, they would eliminate the biggest reason why DUV was superseded by EUV from 7nm onwards. The extra equipment needed for DUV multi-patterning becomes ridiculous once we get to quad patterning, RELATIVE to EUV. Btw, I'm not saying DUV 7nm on FinFET could not compete against 7nm EUV, because it can, but only if it is China's 7nm DUV on FinFET competing against anybody else's 7nm EUV.
If CFET, nVSAFET or some other variation of a vertically integrated architecture were to replace FinFET for DUV, then we have a very interesting situation. What was the entry point for EUV at 7nm, you would now have commercially viable DUV processes to at least 5nm because most of the extra equipment, with most of the associated capital costs, lower yields, greater inefficiency you get with multi-patterned FinFET would be unnecessary. Yes, you would still need more equipment but nothing on the exponential scale that you need with multi-patterning on FinFET. Even more interesting is the following description of nVSAFET.
A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs)
If this works the way it's described, it means that the self-aligning properties of SADP multi-patterning are built-in to this architecture. That means it could scale down to 3nm....and below, until it reaches some thermal threshold where it can't scale any further. Where would that leave EUV? Consider that we are already talking about how advanced packaging will be taking market share from the tail end of EUV 7nm, 5nm process nodes, and that's using FinFET. Now, what happens if you replace FinFET with nVSAFET and scale what would probably at best be packaged 7nm 2.5D/3D FinFET chips with packaged 3nm 2.5D/3D nVSAFET chips? You see where I'm going with this? It could get very, very ugly for TSMC, Samsung and ASML.
Do I think this will happen? Yes, but not anytime soon. Both the CFET and nVSAFET architectures were created and R&D done almost entirely by Chinese teams. This indirectly suggests that China is developing this by themselves and not as part of some larger international initiative. With this comes the main problem which is that EDA software supporting these architectures need to be developed first and its only recently that China had the entire domestic semicon supply chain available, and only fully to 28nm. Which means, it will still take years for such EDA software to complete development in parallel with China's domestic semicon equipment. Until then, forget about seeing anything other than planar, FinFET and GAAFET. I think China's LPP EUV will arrive way before this sees the light of day. It's even possible the SSMB EUV will arrive before this sees first silicon. In any case, China will see it's LPP EUV, SSMB EUV and CFET/nVSAFET designs so it's all good either way.
So from your explanation it's possible, they are researching and improving the DUVL tech with ASML until a viable Chinese EUVL is introduced. Now my question is will these become mainstream and make EUVL redundant?
