Chinese semiconductor industry
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Just generally stupid policy.
I was recently looking at semiconductors used in NEV industry. The leading AI chips used for cars are from Nvidia and Qualcomm I think. A good number of Chinese automakers have placed orders for American chips. But due to the sanction threats, they've also prepared themselves for the possibility of not having access to them. As such, Horizon Robotics, founded just 6 years ago, now have investment from all the major Chinese automakers and probably getting orders from them. The individual processing chips themselves are not as good as Nvidia ones but they are good enough to support L4 driving. And more importantly, they will be able to work with Chinese automakers, far and away the leaders in this field, to continue to improve their chip technology. So, while America could've had dominated this one part of the EV/AV revolution supply chain, they just created a major competitor.
And with all the money coming in from car companies, Horizon will also be able to invest in making AI chips for other fields.
More effort and complexity to achieve smaller benefit. This would actually make it harder to catch up. The differentiation between the have's/have-not's will be magnified. Even very difference in technical or RD capability would be magnified into big delta in the end-resulting metric such as HVM capability and yield.
This is clearly what's happening already, with less players able to conquer FinFET, and a few struggling even with HVM yield. The gap in capability will continue to magnify with migration to GAA nanosheet, to GAA forksheet, to CFET.
@ansy1968, Some of these experts response do not really address the question asked, which I thought is about transition from single to multiple patterning in EUVL and subsequently to HiNA EUVL. I'll take a stab at translating what these "experts" said.
A lot said here. Addressing the last few comments. 193nm to EUV is indeed a revolutionary change compared to 248nm to 193nm to immersion. Introduction of EUV created problems for the photomasks industry that it had to come up with new mask blanks, new ways to make, measure, inspect. Pellicles used to keep the photomask clean has to be completely re-engineered. It's so difficult, I think only a few mask operations in the world have the capability to support EUV reticle manufacturing.
What’s Next In Fab Tool Technologies?
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MAY 12TH, 2021 - BY:
Experts at the Table: Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and other next-generation fab technologies with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpts of that conversation. To view part one of this discussion, click . Part two is .
SE: EUV lithography is in production at the 7nm and 5nm logic nodes. We’ve heard some chipmakers are moving from EUV single patterning to EUV double patterning at 5nm and beyond. From there, we’re expecting to see high-NA EUV, which is in R&D. What are you seeing from your vantage point here?
Fried: If EUV had been deployed on its originally-slated schedule several years earlier, it would have been used as a single patterning scaling replacement and as a stepwise progression from 193nm immersion lithography. Unfortunately, it took longer than expected to get EUV established. This created a continuing need for multiple patterning with 193nm immersion, which includes self-aligned double patterning and self-aligned quad patterning. I worked on some early double-patterning initiatives using a 90nm reticle about 20 years ago, when self-aligned double patterning wasn’t truly viable. At the time, these efforts used a little trick that we played in the lab. Due to EUV taking so long to come to fruition, we built a much more robust version of double-patterning and quad-patterning to fill the void left by the lack of commercial EUV capabilities. EUV is now finally available, but it has come at a time when it can’t just be used as a single-patterning replacement. In several applications, EUV will most likely be deployed as the litho replacement during the litho step in double patterning. EUV still provides a huge advantage, since it will eliminate significant process time and complexity. Usually, these types of lithography scaling changes come with material challenges. I lived through the 248nm to 193nm lithography transition, and it was a difficult transition because many of the materials weren’t fully ready for manufacturing criteria. The equipment at the time was ahead of the materials. With EUV, it’s a little bit different. The equipment took so long to arrive and due to the extremely short wavelength, EUV introduced several unique material challenges. In addition, any stepwise progression in the fab has ripple effects into every other aspect of the fab. However, I believe there are adequate levels of innovation in all semiconductor fabrication sectors to support the progression to EUV along with the next big stepwise progressions.
Going to HiNA EUV will bring about yet another challenge from the anamorphic nature of HiNA EUVL. More on this further down this thread.
Shirley is referring to reticle and wafer inspection in general here. EUV reticle inspection is completely different from before. Transmission mode inspection is the norm for non-EUV reticle inspection. EUV reticle inspection relies on Reflective mode. The current EUV reticle inspection leaves much to be desired at the moment and KLA is supposedly working hard to close that gap.
The latter part about stochastic wafer defects refers to general overall effort by KLA to improve the inspection performance where defect of interests are captured without capturing unwanted nuisance false defects.
Fumimura is talking about the impact from the anamorphic reduction lens of HiNA EUV. Previously the reduction is isomorphic, 4x in both x & y direction. In this case, a defect of the same size (round defect) would be transferred onto the wafer, in theory, the same in both x & y direction or have same printability. For anamorphic case, the same circle defect, will transfer to the wafer in an elliptical shape. Now, this would require the reticle inspection of these HiNA reticles to treat a defect of same size differently. The reticle inspection algorithm would have to figure out what will print what won't print based on the spatial orientation size.
I don't think people have figured out yet on how to quantify the printability of defects for HiNA reticles.
Fried is talking about LAM's work on dry resist. This is is supposed to improve the image contrast and defectively performance for EUV applications. But, my take is this would required a disruptive change to the current way of working. Dry resists have to be CVP onto the wafer. CVP is not part of the track, so implementing dry resist would have a different manufacturing step/flow than the norm. Existing resist makers are also making improvements to provide same depth of focus, high absorption, collapse margin while maintaining the long traditional manufacturing flow. So over the last year, I think the benefit of LAM dry resist doesn't seem as attractive considering the changes needed. I can't speak for others, but I think more often than not, it's safer to make as few changes as possible.
I think Chen is talking about using Source Mask optimization aspect of computational lithography to provide more robust process window to build photomasks. So, optimize the design+OPC on the photomask to allow for good photomask and wafer yield.
Shirley is not talking about EUV specifically. He's talking about the need to inspect and measure of buried features once we go to GAA. For planar & FinFET, you look for defects from the top down, between features. But with GAA, between features all of sudden couldn't be seen from top down. Defects between the nano sheets when looking from top-down are blocked by the nano sheets on top.
Imagine a Chinese professor working in the US with a degree in US History calling for the return of the Confederacy. Why is this guy in HK? It just means the national security law has loopholes.
Founded in July 2018, Shanghai Jingce Semiconductor Technology Co., Ltd. is mainly engaged in the research and development, production and sales of semiconductor testing equipment, and also develops some testing equipment in the field of display and new energy.
Shanghai Jingce Semiconductor Technology Co., Ltd. has achieved technological breakthroughs and industrialization of semiconductor testing and process equipment through independent construction of R&D teams
We have cooperated with a number of well-known R&D centers, universities and colleges to jointly develop new testing solutions and improve the technical level of the domestic semiconductor testing equipment industry.
- High-precision compliant mechanism for lens XY micro-adjustment
ABSTRACT
The high resolution of lithography lenses has led to a requirement for high-precision lens-adjusting compensators. This paper presents the design, analysis, and testing of a high-precision two-degrees-of-freedom compliant mechanism to be used for lens XY micro-adjustment. The monolithic mechanism, which is based on a 1RR–2RRR configuration, uses flexure hinges to connect the movable inner ring with the fixed outer ring. The apparatus is driven using two piezoelectric actuators, and the lens terminal displacement is fed back in real time using two capacitive sensors. This paper describes the principle of the mechanism. Simulations and experiments are then performed to evaluate the system. The results show that the strokes along both the x-axis and the y-axis exceed ±25 µm. The accuracy of the proposed mechanism is better than ±7 nm. The root-mean-square induced figure error is better than 0.051 nm. The coupling z and tip/tilt rigid motions are less than 50 nm and 220 mas, respectively. The first natural frequency of the mechanism is 212 Hz. These results indicate that the mechanism has advantages that include high accuracy, low coupling errors, high rigidity, and compactness and that it will act as an efficient compensator for lithography lenses.
ACKNOWLEDGMENTS
This work was supported by the National Youth Foundation of China (Grant No. 61504142). The authors are also grateful to the Changchun Institute of Optics, Fine Mechanics, and Physics for the use of their equipment.
China's semi industry is headed for major disruption in the market. Over the next 5 years the Chinese semi industry will likely be the market leader in display panels, image sensor chips, discrete semiconductors, automotive, IoT, and power semiconductors. I also expect China to be at least in top 3 in RF and NAND over next 5 years. You can already see it happening as we speak. And SMIC, where it is behind GlobalFoundries in that table, after their two new fabs open this year, will surpass GlobalFoundries which will continue sliding backwards. Once the third SMIC factory opens then it will surely surpass UMC unless UMC decides to go into EUV technology. Something which they thus far have not gone into. In other words I expect China to crowd out the market on anything which does not use EUV. The rest of the players on the market will eventually shrink and lose orders and many will go bankrupt and vanish off the market altogether. EUV machines need to come down in cost if the West's semi industry is to continue in its present form with dozens of players however. Because the current high expense of EUV machines means it will be limited to very few players and eventually you will see concentration of capital and attempts at monopolization. Thus far the existence of foundries like TSMC prevents this. But you are already seeing concentration in the industry with Intel having acquired Altera and now Tower semiconductor. Once Intel goes into EUV and if they do manage to get their foundry business working, you might eventually see Intel start going into an acquisition spree and concentrate into a huge monopoly and this time with the blessing of the US government.
So it is in TSMC's interest that the Chinese chip designers do not go away and that the US does not concentrate the business into just a few of their companies. Otherwise their future might be quite grim indeed. As is the US does not have the technical talent in process technology to compete, nor the proper economic environment for fabs, but they can quite compensate that with unfair monopolization in tools and their leverage of this into design. Much like Intel did in the mid-1980s to kill off their competition in x86. So far there are lots of trends and Intel's move to EUV could still fail. But I see this as a transitional period like early 1990s where RISC dominated x86, only for x86 to dominate RISC again when the Pentium and Pentium Pro came out. There is excessive concentration of the logic market in the US with companies like Intel and Qualcomm.
A supplier of core components for semiconductor manufacturing equipment, Cronos completed B round of financing of nearly 100 million yuan
According to micronet news, recently, Shenzhen Kronos Technology Co., Ltd. (hereinafter referred to as "Cronos") completed the B round of financing of nearly 100 million yuan, and the investor is SMIC Juyuan.
Source: Kronos official website
Official news shows that Cronos' main business is nano-scale and micro-scale linear motor motion platforms, and it is a core component supplier in the semiconductor industry and integrated circuit manufacturing equipment. It is reported that last year, the company released the self-developed "Little Blue Power Rail", which organically combines the motor and the rail, and expands to many industries such as lithium batteries and photovoltaics. At present, Cronos has accumulated more than 7,000 kinds of non-standard platform research and development experience, and its customers are all over the country and in many fields, including semiconductor chips, new energy lithium batteries, solar photovoltaics, etc.
At the end of 2021, Cronos released an ultra-precision air flotation platform with a repeatable positioning accuracy of ±50nm. The ultra-precision air-floating platform can provide a carrier platform that can realize precise positioning, detection and precise movement for wafer cutting, wafer inspection, wafer packaging and other fields. It is an advanced electronic manufacturing equipment, such as a lithography machine placement machine. The main mechanism of the work fully solves the difficult problems of high-precision parts in processing and testing. (Proofreading/Ruobing)
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