Allow me to introduce myself. I have been lurking for a few years. Normally I just watch, listen, learn, and do not comment, but there is just too much incorrect information. Given that it is my own field, I feel compelled to at least provide some correct information. Until 2012, I was a PE (Principal Engineer) at a very large processor company (the one with the letter "I"). There are many details I cannot share as that would violate NDA as well as ITAR.
There is confusion among Architecture, Micro Architecture, Circuit Design, Floorplanning, and Process Technology. These are distinct areas. "Packaging" is also a distinct area, and is mostly not what many seem to think it is.
There is no such thing as something "leaking voltage." Different kinds of transistors behave differently. For CMOS, leakage has always been an issue. This is not new. What is new is how serious the issue has become in the last two decades. There are different kinds of leakage. One is gate leakage. The use of High-K metal gates, specially, the use of hafnium, is around for years (can't say exactly how many), and this largely solves gate leakage. The much more serious issue is source-to-drain leakage. This has been an issue for decades, and is not new, and not specific to the recent process nodes. And CPUs, and circuits in general, can become "unstable" and fail to function properly for many reasons. Again, this is not specific to the recent process nodes.
The transition from 32nm to 28nm was not that hard, relatively speaking. It was certainly not as easy as the earlier transitions, but it was not nearly as hard as the later ones. And, while we are at it, a Xnm process is not always actually Xnm. Today that's often just the name of the process. It does not necessarily indicate the real minimum channel length of the devices.
The so-called TriGate, or, more correctly, FinFET, design has nothing to do with "futher packing of CPU circuitry by going 3 dimensionally." It is a way of constructing transistors. There are many ways to make transistors, even within one kind of transistor. As mentioned before, this is a distinct area from circuit design.
Liquid immersion lithography is not new, and was not really prompted by the latest process node transitions. It was proposed a long time ago and is simply a way of getting the effective wavelength down so that we can do smaller devices while keeping the usual issues of variation, edge coherence, and so on, in check. There are other solutions being worked on, as always.
The "Chinese foundries," meaning mostly SMIC, are indeed behind by about 2 generations. In fact, going by the timeline, they are behind by just over 2 generations. This is actually normal, given where they were before.
Intel is a US company, yes, but it is also very much an international company. Intel has many engineers from both China and India (probably many more than most people believe, just go to the cafeteria and take a look, it would pobably surprise most people). Some of them are now US citizens. Many have Green Cards but are not US citizens. Many are not even permanent residents, they have work visas. And many do not even reside in the US. They work from China and India. The same is true for a number of other large tech companies, particularly those in Silicon Valley. And yes, this often creates problems as there are restrictions in communication, even though often it does not make sense. For example, someone can come up with something, write it up, and after the document has gone through the process, the original author actually cannot read what he wrote.
As for HPC (High Peroformance Computing), or what many call Supercomputing, it is NOT just about hooking up a large number of processors. This is not only factually untrue, it is offensive and insulting to those of us who actually work in the area. Yes, financial resources is of course key, but the most critical aspect of HPC, in terms of design, is the interconnect fabric. Specifically, the Tianhe-2 has a very interesting design. And, more to the point, the control processor used in the fabric is, as far as I know, designed by the Chinese and fabbed by them. So while they are indeed behind in some key areas, for HPC they are actually doing very good work.
There is confusion among Architecture, Micro Architecture, Circuit Design, Floorplanning, and Process Technology. These are distinct areas. "Packaging" is also a distinct area, and is mostly not what many seem to think it is.
There is no such thing as something "leaking voltage." Different kinds of transistors behave differently. For CMOS, leakage has always been an issue. This is not new. What is new is how serious the issue has become in the last two decades. There are different kinds of leakage. One is gate leakage. The use of High-K metal gates, specially, the use of hafnium, is around for years (can't say exactly how many), and this largely solves gate leakage. The much more serious issue is source-to-drain leakage. This has been an issue for decades, and is not new, and not specific to the recent process nodes. And CPUs, and circuits in general, can become "unstable" and fail to function properly for many reasons. Again, this is not specific to the recent process nodes.
The transition from 32nm to 28nm was not that hard, relatively speaking. It was certainly not as easy as the earlier transitions, but it was not nearly as hard as the later ones. And, while we are at it, a Xnm process is not always actually Xnm. Today that's often just the name of the process. It does not necessarily indicate the real minimum channel length of the devices.
The so-called TriGate, or, more correctly, FinFET, design has nothing to do with "futher packing of CPU circuitry by going 3 dimensionally." It is a way of constructing transistors. There are many ways to make transistors, even within one kind of transistor. As mentioned before, this is a distinct area from circuit design.
Liquid immersion lithography is not new, and was not really prompted by the latest process node transitions. It was proposed a long time ago and is simply a way of getting the effective wavelength down so that we can do smaller devices while keeping the usual issues of variation, edge coherence, and so on, in check. There are other solutions being worked on, as always.
The "Chinese foundries," meaning mostly SMIC, are indeed behind by about 2 generations. In fact, going by the timeline, they are behind by just over 2 generations. This is actually normal, given where they were before.
Intel is a US company, yes, but it is also very much an international company. Intel has many engineers from both China and India (probably many more than most people believe, just go to the cafeteria and take a look, it would pobably surprise most people). Some of them are now US citizens. Many have Green Cards but are not US citizens. Many are not even permanent residents, they have work visas. And many do not even reside in the US. They work from China and India. The same is true for a number of other large tech companies, particularly those in Silicon Valley. And yes, this often creates problems as there are restrictions in communication, even though often it does not make sense. For example, someone can come up with something, write it up, and after the document has gone through the process, the original author actually cannot read what he wrote.
As for HPC (High Peroformance Computing), or what many call Supercomputing, it is NOT just about hooking up a large number of processors. This is not only factually untrue, it is offensive and insulting to those of us who actually work in the area. Yes, financial resources is of course key, but the most critical aspect of HPC, in terms of design, is the interconnect fabric. Specifically, the Tianhe-2 has a very interesting design. And, more to the point, the control processor used in the fabric is, as far as I know, designed by the Chinese and fabbed by them. So while they are indeed behind in some key areas, for HPC they are actually doing very good work.
