Chinese Economics Thread

[gelgoog]

That is the whole point though. Since it is a RISC (Reduced Instruction Set Computer) processor.
It also had to be a processor that a one or two student team could design in a semester.

One of the people there in the brainstorming session said he didn't need multiplication and division in his processors (his company made microcontrollers for solid state storage drives) and some of the students didn't want to spend time implementing that either. So that was also made into an extension. Not part of the base ISA. You can implement multiplication in software with shifts and adds anyway.

But you also have the huge (and growing) standard extensions if you want more. And if you want even more instructions you can add your own. That is also possible. None of the other ISAs were designed like this. That definition is to the credit of the Berkeley team really.
Some people in the brainstorming session said this would lead to too much fragmentation in the implementations. But a couple of us came up with the profiles scheme. We "copied" it from the way the OpenGL graphics extensions and standards are defined.

 

[GZDRefugee]

That is the whole point though. Since it is a RISC processor (Reduced Instruction Set Computer).
But you then have the huge (and growing) standard extensions if you want more. And if you want even more instructions you can add your own. That is also possible. None of the other ISAs were designed like this. That definition is to the credit of the Berkeley team really.
Some people in the brainstorming session said this would lead to too much fragmentation in the implementations. But a couple of us came up with the profiles scheme. We copied it from the way the OpenGL extensions and standards are defined.

I understand the minimized instruction set for extensibility reasons. However, having to look around for instruction sets, not finding the ones you want, and being forced to implement it yourself is a large timesink and pain in the ass from a developer's point of view. It's a very personal gripe but I end up having to make up for the slack of coworkers who refuse to learn RISC-V assembly and managers dump more on top of my snowballing-out-of-control responsibilities.

 

[gelgoog]

I understand the minimized instruction set for extensibility reasons. However, having to look around for instruction sets, not finding the ones you want, and being forced to implement it yourself is a large timesink and pain in the ass from a developer's point of view. It's a very personal gripe but I end up having to make up for the slack of coworkers who refuse to learn RISC-V assembly and managers dump more on top of my snowballing-out-of-control responsibilities.

A lot of it can be left to the compiler. It will only be of concern to people writing low level code. And you can pretty much expect RVA22 to be the basic implementation since it is required by Android.

We basically tried to design something that could replace all 32-bit and larger main processor architectures in the market. It has to fit from a tiny microcontroller to a server processor. Well maybe it will get into servers and supercomputers someday. It would be fun to watch. We kinda just made it up for kicks. It kinda snowballed. I had huge expectations because of Patterson's team being well known in the area, but it's surprising how much it grew really.

 

[mossen]

Surprising to see that multiple deaths from crap quality indian drugs isn't getting a huge international outcry. Imagine if it was China.

There were articles written about it last year. Ultimately, India has a narrow human capital base. Its intellectual elites are very capable, but many tend to emigrate to the West. The people who stay back concentrate in high-margin businesses like software exports. Lower margin areas, like generic pharma, get the riff-raff. Same with the aerospace industry. It's not that these are "easy" industries. They just tend to have lower salaries because profit margins tend to be lower overall.

This is a hidden advantage of China. Even if the money isn't always great, there is a very strong "baseline" of talent that even an engineer from a 2nd tier university will probably be pretty damn capable. You can't really say that for India or, increasingly, even many parts of the West.

 

[GZDRefugee]

A lot of it can be left to the compiler. It will only be of concern to people writing low level code. And you can pretty much expect RVA22 to be the basic implementation since it is required by Android.

I guess I am super unlucky having to deal with interfacing a microcontroller with proprietary hardware.

We basically tried to design something that could replace all 32-bit and larger main processor architectures in the market. It has to fit from a tiny microcontroller to a server processor. Well maybe it will get into server and supercomputers someday. It would be fun to watch. We kinda just made it up for kicks. It kinda snowballed. I had huge expectations because of Patterson's team being well known in the area, but it's surprising how much it grew really.

That is cool. I am also looking forwards to widespread adoption. As an insider, do you see any potential issues scaling up to high performance computing?

 

[gelgoog]

I guess I am super unlucky having to deal with interfacing a microcontroller with proprietary hardware.

Well the alternative in the past would likely have involved learning an ISA for each proprietary processor you need to interface with. At least this way, if the architecture proliferates more, the base ISA will be common between processors.

That is cool. I am also looking forwards to widespread adoption. As an insider, do you see any potential issues scaling up to high performance computing?

To be honest when we did the brainstorming I pushed for traits that would allow it to scale up to server applications. 32 registers for example is overkill for an embedded processor and the others were strongly against it. That was when we came up with the embedded profile with just 16 registers for users which don't need it. In tiny processors all those registers would use too much die space. Not having a status register is also supposed to simplify making really wide processors, much wider than you see usually. It is shared state which complicates superscalar processor design. I think the main mistake with the specification is that the memory addressing modes are way too simple. You will need more instructions and code will be less compact to achieve the same results. I also wanted four operand fused multiply-add to be in as an extension from the get go ala Hitachi SH-3-DSP and that wasn't put in. But that one is to be expected. It would mess up a lot of things in the design. I also wouldn't be surprised if Hitachi's implementation back then was still under patent. So we couldn't use the same concept.

The worst obstacle to high performance is the way too simple memory addressing modes I think. It would be nice to see a commonly available high end implementation which did instruction fusion and multi-threading but those aren't available yet. Even though this is part of the overall spec. In retrospect we should have also designed in a multiple register save and restore mechanism similar to that in ARM. But back then I didn't consider that. Probably also patented. We basically couldn't use anything that was developed after the early 1990s.

 

[henrik]

What do you mean how did it go for Apple? Apple is clearly moving more production to India. So you are luxshare, you can either follow suite and keep your work share. Or if you don't do it, that work share goes to Foxconn. What you are saying makes no sense.

As Apple, Foxconn and others learn their lesson in India, they will avoid India like crazy.

 

[Randomuser]

Jai hind right?

 

[horse]

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[curiouscat]

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I’m personally really confident this pivot will go far better than analysts thought it would earlier.