Chinese semiconductor thread II

[Michael90]

Chinese media is restrictive so they usually don't reveal much information only big tools companies like NAURA/AMEC regularly do publish their revenue sheet and number of tools/equipment.. for example, SMIC never disclose their 7nm despite they are producing 7nm for years and going to add massive 7nm capacity this year.

the same method applicable on all High tech fields.

I see. Not sure that’s a good trait. China should have its own major voice and media platforms which are viewed and looked at globally and where most people go to for information when it comes to China. It’s a huge mistake to let your enemies and rivals be your spokesperson globally. lol. When even Chinese people themselves are using western/korean media to get information about China, this is not a good sign .
to be fair, the Chinese government tried abit by setting up CGTN. However it’s just that they suck spectacularly . I’m not even sure who even watches that. Their programs are so boring/bland, some of their journalists don’t even have good/catchy English sometimes(which also matters
I don’t know if China should try something new

 

[interestedseal]

Cambricon too required HBM as they are going to produce decent number of chips this year. 2026 is the breakout year for domestic Ai/GPU chips. so CXMT has to mass produce HBM3 to fulfil the critical gap.

HW is rumored to get dram dies from CXMT and do advanced packaging in house to produce their own HBM. Difficulty of HBM3 is in packaging/stacking, not the D1z dram die itself. HW fabs may actually be more competent than CXMT in advanced packaging

 

[latenlazy]

Yes. In the case of new technologies companies bet.

Different from the NXT2150I in China. We have a case of study:

TSMC is betting that Low NA EUV throughput is going to become high enough that their expertise in multi patterning is going to give them an advantage at a much lower cost.

While Intel and Samsung are betting that getting into High NA EUV earlier is going to give then an advantage over the competition in the near future regardless how expensive it is.

Who is going to win? make your bets.

These are not “bets”. They’re rigorously studied business decisions about which production line design choices yield the best commercial results given where in-house capabilities are at. EUV is also not a “new technology” at this point. It’s been in commercial use for almost a decade. That would be like saying DUVi is a new technology in the early 2010s. If doing more patterning steps with the NXT 2150 offered comparable technical performance or superior operational efficiencies to greater EUV adoption it would be reflected in commercial decisions and we wouldn’t see EUV adoption increase with node shrinks entering high volume production. The bets are done in R&D choices, not commercial operation choices.

 

[sunnymaxi]

HW is rumored to get dram dies from CXMT and do advanced packaging in house to produce their own HBM. Difficulty of HBM3 is in packaging/stacking, not the D1z dram die itself. HW fabs may actually be more competent than CXMT in advanced packaging

interesting if true. Huawei slowly and steadily getting into chip manufacturing so this was expected outcome.

@jx191

 

[tokenanalyst]

Yes. In the case of new technologies companies bet.

Different from the NXT2150I in China. We have a case of study:

TSMC is betting that Low NA EUV throughput is going to become high enough that their expertise in multi patterning is going to give them an advantage at a much lower cost.

While Intel and Samsung are betting that getting into High NA EUV earlier is going to give then an advantage over the competition in the near future regardless how expensive it is.

Who is going to win? make your bets.

Low NA EUV vs High NA EUV. The same thing as with immersion, ones has much lower resolution than the other, one is much mature, one is cheaper, the other is costlier. You may think is better to go with High NA EUV but TSMC think otherwise

These are not “bets”. They’re rigorously studied business decisions about which production line design choices yield the best commercial results given where in-house capabilities are at. The bets are done in R&D choices, not commercial operation choices.

Not "bets" like casino, jesus christ, I mean bets like

TSMC is confident based on their R&D that their wafer processing couple with the increasing throughput of Low NA system is good enough to overcome the difficulties of Low NA EUV multi patterning. Basically they are "betting" on their process capabilities and ASML continuous development of Low NA EUV systems

Intel is "betting' that they have overcome the issues of High NA EUV and even if throughput is lower doing less patterning steps will require less wafer processing.

They are taking a calculated risk and the higher ups are betting on a reward if they get it right.

 

[latenlazy]

Low NA EUV vs High NA EUV. The same thing as with immersion, ones has much lower resolution than the other, one is much mature, one is cheaper, the other is costlier. You may think is better to go with High NA EUV but TSMC think otherwise

You’re talking around the point of contention, which is that there are capabilities with EUV that doing more patterning steps with DUVi cannot effectively substitute for, even with the newest models. If they could we would see adoption of equipment for new lines and process iterations go one way and not another.

Not "bets" like casino, jesus christ, I mean bets like

TSMC is confident based on their R&D that their wafer processing couple with the increasing throughput of Low NA system is good enough to overcome the difficulties of Low NA EUV multi patterning. Basically they are "betting" on their process capabilities and ASML continuous development of Low NA EUV systems

Intel is "betting' that they have overcome the issues of High NA EUV and even if throughput is lower doing less patterning steps will require less wafer processing.

They are taking a calculated risk and the higher ups are betting on a reward if they get it right.

It’s not about “confidence” is my point. These are rigorously studied decisions involving a lot of operational analysis *that are biased against risk*. There is no reward to adopting a higher risk more technically advanced technology and getting the same high volume commercial performance. That’s not how commercial decisions are made. If you think there’s adoption risk you hash it out with your R&D team not in your commercial operations.

 

[tokenanalyst]

You’re talking around the point of contention, which is that there are capabilities with EUV that DUVi cannot effectively substitute for, even with the newest models. If they could we would see adoption of equipment for new lines and process iterations go one way and not another.

I explain you that the new immersion scanners are too recent and the investment in EUV already started with the NXT1980i, there is not going back, the investment is already make.
The NXT2150I was marketed for 3nm, probably for the future Chinese market if the allow to sell ever again. We not going to know until a country like China either develop similar tools or get it from ASML.
Is more precise than EUV scanners. So is entirely possible to reach 3nm equivalent nodes with immersion at a decent yields and even less with lithography resolution enhancement techniques.

These are rigorously studied decisions invoking a lot of operational analysis.

This is where the confidence come, basically calculated risk management.

 

[latenlazy]

I explain you that the new immersion scanners are too recent and the investment in EUV already started with the NXT1980i, there is not going back, the investment is already make.
The NXT2150I was marketed for 3nm, probably for the future Chinese market if the allow to sell ever again. We not going to know until a country like China either develop similar tools or get it from ASML.

New production lines are new investments, not old investments.

Is more precise than EUV scanners. So is entirely possible to reach 3nm equivalent nodes with immersion at a decent yields and even less with lithography resolution enhancement techniques.

If this were true we would see that fact reflected in production design decisions for new production lines.

This is where the confidence come, basically calculated risk management.

Commercial decisions are biased *against* risk.

 

[tokenanalyst]

NXT:2100 has already an insane overlay and cross matching capabilities with EUV.


2150i is 15% better than that.


NXT:2050i is good enough for a 5nm process node and NXT:1980i is good enough for 7nm process node. Just do the math.

 

[latenlazy]

NXT:2100 has already an insane overlay and cross matching capabilities with EUV.

View attachment 175231
2150i is 15% better than that.
View attachment 175232

NXT:2050i is good enough for a 5nm process node and NXT:1980i is good enough for 7nm process node. Just do the math.

Single pass error is not the same thing as error stack from multiple passes. The issue with trying to replicate each EUV patterning step with 2-4 additional patterning steps using DUVi is about error stack from multiplying the number of pass throughs, not about the inherent accuracy of the instrument itself. Like yes, using EUV for 5 nm and below also requires multipatterning, but you are still doing multiples fewer patterning steps than with DUVi, which means much lower error stacking multipliers from additional patterning steps. Using your own language here “just do the math”. This is pretty fundamental to the point I’ve been trying to highlight.