High Density Stacked Dual Channel IGZO FET 3D DRAM with Vertical BL: Process Integration, Simulation and Scalability
Beijing Superstring Academy of Memory Technology, Beijing, China
Abstract:
IGZO based dual channel FET monolithic 3D DRAM architecture with vertical bit line (IGZO-VBL) is proposed in this work. The architecture design, process integration, electrical TCAD simulation and circuit design simulation are systematically investigated. The BL, WL and IGZO channel related coupling capacitance are evaluated based on the same cell architecture but different feature sizes. Furtherly, layer-layer isolation space and work function of source/drain metal are discussed to minimize passing gate effect and channel-source/drain contact barrier. The IGZO channel shows ultra-low Ioff due to its large bandgap, which is conductive to data retention. In addition, we evaluate the bitcell density, BL sensing signal, WL turn-on delay time and cell array area ratio with different cell number per WL and layer number. Considering feasible integration process, especially no channel doping, acceptable BL sensing signal and reasonable circuit design, this IGZO-VBL architecture offers a pathway to achieve promising stackable monolithic 3D DRAM with ultra-high density and low cost.
