Chinese semiconductor thread II
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I keep telling people that Chinese chip designers are not necessarily using TSMC process for a lot of the AI stuff. TSMC is fully booked and Samsung is eager for more customers. Also Samsung can provide memory chips. Not saying that BYD is necessarily using Samsung for Xuanji A3, but that both TSMC and Samsung are options.
SMIC's own capacity and future domestic ones are going to be fully booked by Huawei and domestic AI chip producers for a while. I would imagine Huawei by itself will need 150k wpm of 5-7nm capacity.
First Micro has secured tens of millions of yuan in Series B++ funding. It is a leading company in the automotive SerDes chip field.
First Microelectronics, a leading manufacturer of automotive SerDes chips, has secured tens of millions of yuan in its Series B++ financing round from key investors including Longcheng Science and Technology Innovation Fund, Suzhou Dunjun, and Nuohui Fund under Changzhou Financial Holdings. Founded in 2021, the company boasts a core team with over 20 years of combined experience from international semiconductor giants, specializing in ultra-high-speed transmission chips critical for In-Vehicle Networks (IVN). These "nerve centers" ensure reliable high-speed data flow between vehicle sensors, controllers, and displays, playing an indispensable role in the safety and functionality of intelligent driving systems and smart cockpits.
The financing marks a significant milestone as First Microelectronics deepens its integration into major automotive supply chains, specifically with Geely. The company successfully debuted its independent chip in July 2025 on the Lynk & Co 06 model and achieved mass production for the Galaxy Star Wish by January 2026. This rapid progression underscores the growing momentum of domestic substitution in the automotive semiconductor sector. Backed by Changjin Holdings, which supports open and compatible multi-protocol technologies, First Microelectronics is poised to accelerate its transition from R&D breakthroughs to large-scale industrial application amidst global supply chain reshaping.
From Defects to Breakthrough: Sanan Optoelectronics Joins Forces with Xi'an University of Technology and Other Industry-Academia-Research Collaborators to Overcome Key Technologies in Gallium Oxide Epitaxy
Sanan Optoelectronics has achieved a significant milestone in gallium oxide (Ga₂O₃) semiconductor technology by solving the long-standing challenge of homoeptaxial growth defects. Through a collaborative effort with Xi'an University of Technology, the National Engineering Research Center for Wide Bandgap Semiconductors (Xian University of Electronic Science and Technology), and Hangzhou Gallium Semiconductor Co., Ltd., the team successfully developed high-quality Ga₂O₃ epitaxial layers on 2-inch substrates using Metal-Organic Chemical Vapor Deposition (MOCVD).
- Defect Suppression: The team precisely optimized nucleation conditions to effectively suppress twin defects, which previously hindered mass production.
- Superior Crystal Quality:The resulting wafers exhibit:
- RMS surface roughness of less than 0.5 nm.
- Electron mobility reaching 100 cm²/(V·s).
- Crystal quality comparable to the substrate itself.
Building on these materials, the team developed lateral power devices, which are better suited for Ga₂O₃'s semi-insulating properties compared to difficult-to-dope vertical structures:
- Breakdown Voltage: Successfully demonstrated a voltage withstand capability of 1420V.
- Switching Characteristics: Achieved an on/off ratio of 10⁵ and threshold voltage uniformity exceeding 91% without requiring complex termination structures.
- Compatibility: The design maintains high compatibility with existing silicon planar processes.
This collaboration marks a transition from material advantage to industrial readiness for Ga₂O₃, a critical "fourth-generation" semiconductor material for high-voltage applications (e.g., new energy vehicles, smart grids, and rail transit). The team has established the process foundation to scale up production from 2-inch to 6-inch substrates, providing essential technical support for the commercialization of next-generation power electronics.
Oriental Crystal Source: AI-powered multi-level process feedback system solves the challenge of improving yield in advanced processes
At the recent 10th ICMI Conference in Shanghai, Dr. Ding Ming, Vice President of Orient Crystal (Dongfang Jingyuan), addressed the critical challenge of yield loss in advanced semiconductor manufacturing. As chip fabrication progresses to the 2nm node, systemic yield losses related to patterning have significantly surpassed random defects. Traditional, experience-based optimization models that rely on manual analysis and fixed rules are no longer sufficient to handle the increasing process complexity, massive data volumes, and the need for early defect prediction, creating a major bottleneck for the integrated circuit industry.
To overcome these limitations, Orient Crystal is deeply integrating AI technology with Electronic Design Automation (EDA) tools to build a model-based, AI-enabled multi-level process feedback system. This solution is centered around the company's independently developed PanGen® computational lithography platform. By leveraging AI for automatic data analysis and predictive modeling, Orient Crystal provides a comprehensive yield management ecosystem, offering tailored computational lithography solutions for both mature nodes and advanced nodes using GPU acceleration and Inverse Lithography Technology (ILT).
The core of this AI-driven solution is the "PanGen Total Mask" series, which enables closed-loop optimization across all manufacturing stages. The suite includes DMC (Design Manufacturability Check), which uses AI to predict process contours and defects up to 100 times faster than traditional methods; PHD (Patterning Hotspot Detection), which dynamically predicts mask-stage defects using SEM data; vPWQ (virtual Process Window Qualification), which combines physical and AI models to improve accuracy during the etching stage; and RUI (Repair Using ILT), which applies pixel-based optimization to correct ultra-advanced process hotspots at the 5nm node and below.
Looking ahead, Orient Crystal plans to optimize its software's user-friendliness and deeply integrate it with its own quantitative testing equipment. This will create a seamless hardware-software closed loop where AI both identifies and corrects manufacturing defects. At the concurrent Microelectronics Semiconductor Exhibition, the company also showcased other proprietary tools, including PanGen Sim®, YieldBook, and electron beam metrology equipment. Through these innovations, Orient Crystal aims to build a comprehensive "GoldenFlow" for domestic chip manufacturing and establish itself as a global leader in integrated circuit yield management.
To overcome these limitations, Orient Crystal is deeply integrating AI technology with Electronic Design Automation (EDA) tools to build a model-based, AI-enabled multi-level process feedback system. This solution is centered around the company's independently developed PanGen® computational lithography platform. By leveraging AI for automatic data analysis and predictive modeling, Orient Crystal provides a comprehensive yield management ecosystem, offering tailored computational lithography solutions for both mature nodes and advanced nodes using GPU acceleration and Inverse Lithography Technology (ILT).
The core of this AI-driven solution is the "PanGen Total Mask" series, which enables closed-loop optimization across all manufacturing stages. The suite includes DMC (Design Manufacturability Check), which uses AI to predict process contours and defects up to 100 times faster than traditional methods; PHD (Patterning Hotspot Detection), which dynamically predicts mask-stage defects using SEM data; vPWQ (virtual Process Window Qualification), which combines physical and AI models to improve accuracy during the etching stage; and RUI (Repair Using ILT), which applies pixel-based optimization to correct ultra-advanced process hotspots at the 5nm node and below.
Looking ahead, Orient Crystal plans to optimize its software's user-friendliness and deeply integrate it with its own quantitative testing equipment. This will create a seamless hardware-software closed loop where AI both identifies and corrects manufacturing defects. At the concurrent Microelectronics Semiconductor Exhibition, the company also showcased other proprietary tools, including PanGen Sim®, YieldBook, and electron beam metrology equipment. Through these innovations, Orient Crystal aims to build a comprehensive "GoldenFlow" for domestic chip manufacturing and establish itself as a global leader in integrated circuit yield management.
Huifeng Diamond Baotou CVD Diamond Heat Dissipation Project Commences
Recently, the Huifeng Diamond CVD diamond heat dissipation project was launched in Baotou.
It is understood that the project focuses on two core areas: CVD diamond semiconductor heat dissipation materials and cultured diamonds, with a total investment of 1 billion yuan. The overall implementation period is planned to be 3-5 years, and the capacity building and market expansion will be steadily promoted in two phases.
According to reports, Huifeng Diamonds' Baotou project fills the domestic gap in high-end semiconductor heat dissipation material production capacity, meets the needs of the chip industry, and seizes the opportunity of expanding consumption of lab-grown diamonds to continuously output high-quality, cost-effective diamond products. It is in line with the trend of domestic semiconductor substitution and the upgrading of lab-grown diamond consumption, and has broad development prospects.
It is understood that the project focuses on two core areas: CVD diamond semiconductor heat dissipation materials and cultured diamonds, with a total investment of 1 billion yuan. The overall implementation period is planned to be 3-5 years, and the capacity building and market expansion will be steadily promoted in two phases.
According to reports, Huifeng Diamonds' Baotou project fills the domestic gap in high-end semiconductor heat dissipation material production capacity, meets the needs of the chip industry, and seizes the opportunity of expanding consumption of lab-grown diamonds to continuously output high-quality, cost-effective diamond products. It is in line with the trend of domestic semiconductor substitution and the upgrading of lab-grown diamond consumption, and has broad development prospects.
The Jiufengshan Semiconductor Manufacturing Base project, with a total investment of 5.2 billion yuan, has launched its bidding process.
Recently, the EPC (Engineering, Procurement, and Construction) project for the Jiufengshan Semiconductor Manufacturing Base was officially launched for bidding. The project is located south of Keji Road and east of Suhu Road, with a planned construction period of 730 days and a total investment of approximately 5.2 billion yuan.
It is understood that this project is a core component of the Jiufengshan Science and Technology Park. The Jiufengshan Science and Technology Park, which was signed and settled in Optics Valley in April this year, has a total construction area of 353,000 square meters and can accommodate advanced production lines such as 8-inch MEMS and 12-inch silicon-based gallium nitride. The entire park is expected to be completed and put into operation in June 2028.
Currently, the compound semiconductor industry innovation block, centered on Jiufeng Mountain Laboratory and covering an area of approximately 14 square kilometers, is progressing at full speed. A 168,000-square-meter incubation, acceleration, and manufacturing base is about to be completed, and efforts are being made to attract and cultivate 100 upstream and downstream enterprises within three years.
It is understood that this project is a core component of the Jiufengshan Science and Technology Park. The Jiufengshan Science and Technology Park, which was signed and settled in Optics Valley in April this year, has a total construction area of 353,000 square meters and can accommodate advanced production lines such as 8-inch MEMS and 12-inch silicon-based gallium nitride. The entire park is expected to be completed and put into operation in June 2028.
Currently, the compound semiconductor industry innovation block, centered on Jiufeng Mountain Laboratory and covering an area of approximately 14 square kilometers, is progressing at full speed. A 168,000-square-meter incubation, acceleration, and manufacturing base is about to be completed, and efforts are being made to attract and cultivate 100 upstream and downstream enterprises within three years.
The first CDSEM unit from the 48th Research Institute of China Electronics Technology Group Corporation was successfully shipped.
The first critical dimension measurement equipment (CDSEM) independently developed by the 48th Research Institute completed the overall debugging and factory inspection, and was officially shipped to the customer.
CDSEM is an indispensable core quantity inspection equipment in advanced semiconductor processes, hailed as the "nanoscale ruler" of semiconductor manufacturing. It can meet the R&D and production inspection needs of cutting-edge fields such as advanced integrated circuits, quantum information, artificial intelligence chips, and optoelectronics. Relying on the "three beams" core technologies, the 48th Research Institute has formed an integrated R&D, production, and service collaborative research team. Through collective wisdom and continuous breakthroughs, it has successively overcome several key core technologies such as high-resolution electron optical systems and high-precision displacement stages, achieving a leap from principle verification and prototype development to engineering products.
This shipment of CDSEM fills a product gap in the semiconductor metrology and inspection equipment field at Institute 48, establishing an electron beam product matrix that integrates manufacturing equipment and metrology and inspection equipment, and creating an independent supporting system for semiconductor micro-nano manufacturing from "processing" to "inspection". As the fifth electron beam device shipped from the institute, the product's maturity, stability, and production capacity have been continuously upgraded, laying a solid foundation for large-scale, standardized manufacturing and continuous delivery.
Next, the 48th Research Institute will take this CDSEM delivery as a new starting point, continue to deepen technological iteration and process innovation, accelerate the industrialization of electron beam equipment and the construction of a service standardization system, strengthen collaborative cooperation with leading enterprises in the industry chain, and contribute to the high-quality development of my country's semiconductor industry with "three-beam" equipment.
Naura is now the second company in China with Ion Beam etching tools for semiconductors. Thought their seems to made for throughput.
As integrated circuit manufacturing processes advance to advanced nodes, chip feature sizes are reaching the atomic level, placing stringent demands on processing precision, surface quality, and damage control. Traditional chemical mechanical polishing (CMP) and plasma etching suffer from drawbacks such as scratches, subsurface damage, and limited precision, failing to meet the core requirements of advanced logic, memory, and silicon photonics chips. Against this backdrop, ion beam etching, with its atomic-level precision and near-zero damage advantages, has become a key process equipment in post-Moore's Law semiconductor manufacturing.
Ion beam etching, superior to traditional processes, highlights its value.
Traditional plasma etching relies on chemical reactions and ion bombardment to remove materials, while ion beam etching accelerates and neutralizes ions before directly bombarding the wafer surface, relying on physical sputtering to remove materials. The difference in their underlying principles determines the performance gap. Compared to traditional processes, cluster ion beam etching offers nanometer-level precision, better directionality, and near-zero damage processing; it is adaptable to almost all materials, offers greater process flexibility, and can fulfill complex requirements such as localized precision finishing of wafers and etching at arbitrary angles.
Overcoming three major technologies and establishing a firm foothold in innovation
Acme Glaion130 has successfully overcome three major technical challenges in the industry, achieving independent development of key technologies:
Gas cluster ion source technology: Compared with conventional single-cell ion source technology, it has a faster etching rate, better surface quality, and lower process damage; the stability and beam quality of cluster ion sources reach a better level than similar equipment, providing core support for atomic-level etching.
Electrode technology under high-speed motion: It enables precise and rapid positioning of wafers, solves the stability problem under high-speed motion, and ensures processing accuracy.
Dynamic precision control algorithm: Equipped with an in-situ film thickness measurement device, it forms the required etching map and optimizes the stage movement trajectory to achieve local fixed-point precision finishing of the wafer.
Ion beam etching, superior to traditional processes, highlights its value.
Traditional plasma etching relies on chemical reactions and ion bombardment to remove materials, while ion beam etching accelerates and neutralizes ions before directly bombarding the wafer surface, relying on physical sputtering to remove materials. The difference in their underlying principles determines the performance gap. Compared to traditional processes, cluster ion beam etching offers nanometer-level precision, better directionality, and near-zero damage processing; it is adaptable to almost all materials, offers greater process flexibility, and can fulfill complex requirements such as localized precision finishing of wafers and etching at arbitrary angles.
Overcoming three major technologies and establishing a firm foothold in innovation
Acme Glaion130 has successfully overcome three major technical challenges in the industry, achieving independent development of key technologies:
Gas cluster ion source technology: Compared with conventional single-cell ion source technology, it has a faster etching rate, better surface quality, and lower process damage; the stability and beam quality of cluster ion sources reach a better level than similar equipment, providing core support for atomic-level etching.
Electrode technology under high-speed motion: It enables precise and rapid positioning of wafers, solves the stability problem under high-speed motion, and ensures processing accuracy.
Dynamic precision control algorithm: Equipped with an in-situ film thickness measurement device, it forms the required etching map and optimizes the stage movement trajectory to achieve local fixed-point precision finishing of the wafer.
The other company is Leuven Instruments.
Threshold Voltage Control Techniques for Advanced Nodes
Beijing NAURA Microelectronics Equipment Co. Ltd, Beijing, ChinaAbstract:
Multi-Threshold-Voltage (Multi-VT) technology serves as a cornerstone for balancing performance and power in advanced CMOS nodes. This work systematically reviews scalable VT control techniques for FinFET and gate-all-around (GAA) architectures, with a focus on work-function metal (WFM) thickness tuning and interfacial dipole engineering. For GAA devices, the stringent Tsus constraint necessitates "zero-thickness" dipole engineering, categorized via integration strategy and assessed in terms of VT shift efficiency, EOT penalty, and reliability. Novel dipole materials (rare-earth oxides, ZrO) are also addressed. This study offers critical insights into Multi-VT implementation for sub-5 nm technology nodes.