Chinese semiconductor thread II

[tokenanalyst]

More CXMT work in nextgen DRAM development. Breaking through the scaling wall.

Innovative DRAM Cell Featuring a Vertical Junctionless Pillar Access Transistor With a High Work-Function Molybdenum Nitride Metal Gate for Enhanced Performance and Efficiency​

Abstract:​

In this work, we demonstrate an innovative dynamic random access memory (DRAM) cell design featuring a vertical junctionless pillar access transistor with a high work-function (WF) molybdenum nitride (MoN) metal gate, enabling enhanced performance and efficiency. By depositing MoN over the gate dielectric at temperatures below 600 ∘ C, we achieved a wrapped-gate transistor array with significantly improved electrical characteristics. Compared to conventional titanium nitride (TiN) gates, the MoN gate exhibits a 0.22-V positive shift in flat-band voltage (VFB) to −0.38 V and a 35% increase in threshold voltage ( Vth) to 0.35 V while maintaining identical on-state current (7.6 μ A/cell) and subthreshold swing (SS) (82.3 mV/dec). These advancements address critical challenges in DRAM scaling, including leakage reduction and noise immunity, without compromising device performance. The MoN gate’s superior WF ( Φm) enables enhanced depletion in the n-type doped channel, ensuring stable operation at 3.3 V with a projected lifetime exceeding ten years. This study establishes MoN as a promising gate material for high-performance vertical junctionless pillar transistors, offering a scalable solution for next-generation 1T1C DRAM architectures.​

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[tokenanalyst]

so far top 3 giants Samsung , Sk Hynix and Micron hesitant to adapt EUV coz of astronomical cost involved in EUV though this could solve the multi patterning issue but memory manufacturers are still prioritizing older and cheaper methods.

Samsung and SK Hynix are focused on developing 3D DRAM and shrinking architectures rather than just shrinking the old 2D designs with EUV.

this is good for CXMT as their competitors still using old but reliable DUVi machines.

LowNA EUV doesn't offer A HUGE advantage against immersion, some, but not huge, the resolution of EUV system is affected by stochastic (random) effects and the productivity is not necessary as high. You still need do double patterning with LowNA EUV at way lower output. better than with quadruple patterning but immersion compensate with higher output.

 

[latenlazy]

LowNA EUV doesn't offer A HUGE advantage against immersion, some, but not huge, the resolution of EUV system is affected by stochastic (random) effects and the productivity is not necessary as high. You still need do double patterning with LowNA EUV at way lower output. better than with quadruple patterning but immersion compensate with higher output.

Higher output can’t compensate for lower tolerances.

 

[tokenanalyst]

Higher output can’t compensate for lower tolerances.

I guess you are referring to geometrical tolerances. Those are defined by device designer. QP, DP, self alignment, EUV or Immersion doesn't matter as long you can reach your parameters.

There is were the stochastic part eats EUV. The resolution is not the 14nm that is marketed, because these random defects many companies are using double patterning. Immersion is already very mature technology and a lot the positioning sensors are shared between immersion. There is a reason why ASML rushed highNA EUV because the difference between lowNA and immersion was not that big.

NOW, lowNA is getting a bit better. The productivity is advancing, resist is advancing, learning curve flattening but the difference, again, is not as huge compared with immersion.

 

[latenlazy]

I guess you are referring to geometrical tolerances. Those are defined by device designer. QP, DP, self alignment, EUV or Immersion doesn't matter as long you can reach your parameters.

There is were the stochastic part eats EUV. The resolution is not the 14nm that is marketed, because these random defects many companies are using double patterning. Immersion is already very mature technology and a lot the positioning sensors are shared between immersion. There is a reason why ASML rushed highNA EUV because the difference between lowNA and immersion was not that big.

NOW, lowNA is getting a bit better. The productivity is advancing, resist is advancing, learning curve flattening but the difference, again, is not as huge compared with immersion.

I’m referring to overall tolerance budget. Each extra patterning step adds potential overlay deviations. The shot noise issues with EUV are certainly a headache but they’re not *as* big a headache as 2-4x increase in likelihood of out of tolerance defects from adding more patterning steps. For volume production one of these error sources scale better than the other. There’s a reason why even though no one likes the cost of using EUV no one is trying to substitute their EUV lines with all DUV processes. We can also see this in how much Huawei and SMIC have been struggling to get to a proper 5 nm process at high yields just by squeezing DUV only processes.

 

[tokenanalyst]

I’m referring to overall tolerance budget. Each extra patterning step adds potential overlay deviations.

Well multiple patterning is already mature, chemical lithography is advancing fast and overlay control metrology tools getting are better. I mean you still have to do multiple patterning with LowNA EUV and the deal stochastic issues at the same time. There is a steep learning curve with EUV.

 

[latenlazy]

Well multiple patterning is already mature, chemical lithography is advancing fast and overlay control metrology tools getting are better. I mean you still have to do multiple patterning with LowNA EUV and the deal stochastic issues at the same time. There is a steep learning curve with EUV.

Yes but the number of additional steps is what matters for defect statistics scaling. If you can do 2-4x fewer steps you are dealing with 2-4x less out of tolerance errors in your defect statistics. Again, this is why no one is trying to do all DUV for sub 10 nm processes if they can help it. EUV has its own set of headaches but the level of capability gain here is not modest.

 

[tokenanalyst]

I’m referring to overall tolerance budget. Each extra patterning step adds potential overlay deviations. The shot noise issues with EUV are certainly a headache but they’re not *as* big a headache as 2-4x increase in likelihood of out of tolerance defects from adding more patterning steps. For volume production one of these error sources scale better than the other. There’s a reason why even though no one likes the cost of using EUV no one is trying to substitute their EUV lines with all DUV processes. We can also see this in how much Huawei and SMIC have been struggling to get to a proper 5 nm process at high yields just by squeezing DUV only processes.

Well is a learning curve, you are not going back after investing dozen billion dollars in lithography equipment.

I Think TSMC because their experience with immersion they are more capable of dealing the issues of multiple patterning EUV, they are in the other side of the curve already, but everyone else is probably looking at High-NA regardless of cost, they can't cope with multiple patterning EUV.
The Koreans are already saying "f*ck that I pay more". While TSMC masochist engineers are saying "give me more pain". CXMT is literally scaling using immersion and some lithography enhancing techniques.

Advancing DRAM patterning: high-NA EUV lithography for 10nm and beyond node technologies​

​

Abstract​

In recent years, the implementation of high-NA EUV has gained significant attention as a potential solution to the resolution limit at ions of low-NA EUV lithography technology. In particular, the use of high-NA EUV enables the transition of low-NA EUV multi-patterning (MPT) layers into high-NA EUV single patterning (SET), thereby reducing the overall number of process steps. Given the significant potential associated with process step reduction, the storage node pad (SNP) layer with bit-line periphery on a single mask, and storage node (SN) layer for 10 nm and sub-10 nm DRAM were selected as the primary evaluation targets in this study. TWINSCAN EXE:5000 scanner in ASML-IMEC high-NA EUV Joint Lab was employed to evaluate its patterning performance. In order to fully utilize the advantage of extended resolution and manage risks of depth of focus (DOF), source and mask were carefully selected through simulat ion, and process parameters such as photoresist, post exposure bake temperature and development recipe were optimized. We demonstrate comprehensive patterning results of high-NA EUV at 10 nm and sub-10 nm DRAM layers, including DOF, massive verification of local CD uniformity (LCDU) at ADI and ACI, and ACI defect inspection. Switching from the low-NA EUV MPT scheme to the high-NA EUV SET scheme significantly reduces the number of process steps, potentially bringing cost reductions. This preliminary result supports the feasibility of applying high-NA EUV to DRAM device.​

 

[latenlazy]

Well is a learning curve, you are not going back after investing dozen billion dollars in lithography equipment.

I Think TSMC because their experience with immersion they are more capable of dealing the issues of multiple patterning EUV, they are in the other side of the curve already, but everyone else is probably looking at High-NA regardless of cost, they can't cope with multiple patterning EUV.
The Koreans are already saying "f*ck that I pay more". While TSMC masochist engineers are saying "give me more pain". CXMT is literally scaling using immersion and some lithography enhancing techniques.

The learning curve for adding multiples of extra steps to stay with DUVi are not low either, and we can pretty much see which one is actually harder and yielding worse results from real world performance with different production lines. Just to re-emphasize this point I don’t think the last two years of process iterations we’ve seen coming out of the Huawei-SMIC partnership relative to the speed at which other fabs moved to 5 nm using EUV supports the idea that the effective performance difference between DUVi with multi-patterning and EUV are modest.

 

[gotodistance]

from April month.. this is Korean Media

1. CXMT (DRAM 및 HBM)
• 2024: ~100,000 WPM level
• 2025: ~200,000 WPM
• 2026: ~300,000 WPM target = Top 3 global rankings
• 2027: 350,000-400,000 WPM
A structure that quickly approaches the level of Samsung (500,000) and Hynix (400,000)
CXMT aims to improve constitution and economies of scale at the same time, with high value-added lines centered on DDR5 and HBM (High Bandwidth Memory) rather than traditional DDR4.
• Shanghai New Fab Construction: It is building a production facility in Shanghai that is two to three times larger than Hefei's headquarters, with the goal of operating it in 2027. Equipment imports will begin in the second half of 2026.
· Target to Expand Production Capacity: We have already expanded our DRAM production capacity from 105,000 units per month at the end of 2023 to 250,000 to 270,000 units per month. With the expansion of the Shanghai plant, our production capacity is expected to double or triple its current capacity.
• Securing HBM Exclusive Line: By 2026, we plan to allocate approximately **20%** of total production capacity to mass production of HBM3 modules. Target wafer input is known to be around 60,000 units per month.
• Hefei Phase 2 Expansion: It will secure 40,000 additional production capacity per month through the Phase 2 expansion of its existing Hefei plant, bringing its total production to over 300,000 units per month.
• Technology Node: To avoid regulation, we are continuing to introduce equipment, naming the 17nm process 18.5nm class, and we are rapidly transitioning our lines to high-performance products such as DDR5-8000 and LPDDR5X.

1. CXMT (DRAM 및 HBM)
• 2024: ~100,000 WPM level
• 2025: ~250,000 WPM
• 2026: ~300,000 WPM target = Top 4 global rankings
• 2027: ~400,000 WPM (Shanghai)
• 2028: ~500,000 WPM (Shanghai)

A structure that quickly approaches the level of Samsung (650,000) and Hynix (500,000)
CXMT aims to improve constitution and economies of scale at the same time, with high value-added lines centered on DDR5 and HBM (High Bandwidth Memory) rather than traditional DDR4.
• Shanghai New Fab Construction: It is building a production facility in Shanghai that is two to three times larger than Hefei's headquarters, with the goal of operating it in 2027. Equipment imports will begin in the second half of 2026.
I have it.
· The Hefei plant's monthly production capacity is 110,000, the second plant's 80,000 and the Beijing plant's 70,000 units, totaling about 300,000 units, all with maximum production capacity.
· In terms of processes, G4 has already been mass-produced at 16 nanometers, with the yield of DDR5 increasing from 80% at the end of 2024 to the current 90% range.
G5 is equivalent to 15 nanometers mass-produced at the end of 2026.
· HBM2 was launched in the second half of 2025 and was primarily supplied to Huawei STEU 910, two years earlier than external expectations. HBM3's front-end wafer production capacity is mainly secured from existing bases in Hefei and Beijing, with a target monthly production of 60,000 units, accounting for about 20% of the total production capacity. The stacking and packaging at the rear end will be undertaken by the newly built HBM encapsulation plant in Shanghai and will be operational at the end of 2026.
• Technology Node: DDR5 (up to 8000Mbps) and LPDDR5X (up to 10667Mbps) offerings (November 2025) Recently, we are quickly transitioning our lines to high-performance product lines such as DDR5-8000 and LPDDR5X.